Semiconductor device
A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.
1. A semiconductor device, comprising:
a substrate;
a channel pattern on the substrate, the channel pattern including a plurality of semiconductor patterns that are spaced apart from each other and stacked on the substrate;
a first source/drain pattern and a second source/drain pattern that are on the substrate, the channel pattern being between the first and second source/drain patterns and connecting them to each other;
a gate electrode on the channel pattern; and
an inner electrode structure between the substrate and a lowermost one of the plurality of semiconductor patterns,
wherein the inner electrode structure includes:
an inner electrode that is a portion of the gate electrode interposed between the substrate and the lowermost one of the plurality of semiconductor patterns,
a first barrier insulating pattern between the inner electrode and the first source/drain pattern; and
a second barrier insulating pattern between the inner electrode and the second source/drain pattern,
wherein an upper portion of the inner electrode structure has a first width, and
wherein a lower portion of the inner electrode structure has a second width that is different from the first width.
2. The semiconductor device of claim 1 , wherein the inner electrode structure further includes a gate dielectric pattern surrounding the inner electrode and being between the first and second barrier insulating patterns.
3. The semiconductor device of claim 1 , wherein each of the first and second source/drain patterns includes an n-type impurity region.
4. The semiconductor device of claim 1 , wherein the second width is greater than the first width.
5. The semiconductor device of claim 4 , wherein a width of the inner electrode structure increases with decreasing distance from a bottom surface of the substrate.
6. The semiconductor device of claim 1 , wherein the first width corresponds to a first distance between the first and second source/drain patterns at the upper portion of the inner electrode structure, and
wherein the second width corresponds to a second distance between the first and second source/drain patterns at the lower portion of the inner electrode structure.
7. The semiconductor device of claim 1 , wherein each of the first and second source/drain patterns includes a lower part in contact with the substrate and the inner electrode structure, and
wherein a width of the lower part decreases with decreasing distance from a bottom surface of the substrate.
8. The semiconductor device of claim 7 , wherein an interface between the lower part and the substrate has a rounded shape.
9. The semiconductor device of claim 7 , wherein an interface between the lower part and the inner electrode structure has a rounded shape.
10. A semiconductor device, comprising:
a substrate;
a channel pattern on the substrate, the channel pattern including a first semiconductor pattern and a second semiconductor pattern that are sequentially stacked on the substrate;
a first source/drain pattern and a second source/drain pattern that are on the substrate, the channel pattern being between the first and second source/drain patterns and connecting them to each other;
a gate electrode on the channel pattern;
a first inner electrode structure between the substrate and the first semiconductor pattern; and
a second inner electrode structure between the first semiconductor pattern and the second semiconductor pattern,
wherein the first inner electrode structure includes:
a first inner electrode that is a first portion of the gate electrode interposed between the substrate and the first semiconductor pattern,
a first barrier insulating pattern between the first inner electrode and the first source/drain pattern; and
a second barrier insulating pattern between the first inner electrode and the second source/drain pattern,
wherein the second inner electrode structure includes:
a second inner electrode that is a second portion of the gate electrode interposed between the first semiconductor pattern and the second semiconductor pattern,
a third barrier insulating pattern between the second inner electrode and the first source/drain pattern; and
a fourth barrier insulating pattern between the second inner electrode and the second source/drain pattern,
wherein a maximum width of the first inner electrode structure is greater than a maximum width of the second inner electrode structure.
11. The semiconductor device of claim 10 , wherein an upper portion of the first inner electrode structure has a first width, and
wherein a lower portion of the first inner electrode structure has a second width that is different from the first width.
12. The semiconductor device of claim 11 , wherein the second width is greater than the first width.
13. The semiconductor device of claim 10 , wherein each of the first and second source/drain patterns includes an n-type impurity region.
14. The semiconductor device of claim 10 , wherein each of the first and second source/drain patterns includes a lower part in contact with the substrate and the first inner electrode structure, and
wherein a width of the lower part decreases with decreasing distance from a bottom surface of the substrate.
15. The semiconductor device of claim 14 , wherein an interface between the lower part and the substrate has a rounded shape.
16. The semiconductor device of claim 14 , wherein an interface between the lower part and the first inner electrode structure has a rounded shape.
17. A semiconductor device, comprising:
a substrate;
a channel pattern on the substrate, the channel pattern including a first semiconductor pattern and a second semiconductor pattern that are sequentially stacked on the substrate;
a first source/drain pattern and a second source/drain pattern that are on the substrate, the channel pattern being between the first and second source/drain patterns and connecting them to each other;
a gate electrode on the channel pattern;
a first inner electrode structure between the substrate and the first semiconductor pattern; and
a second inner electrode structure between the first semiconductor pattern and the second semiconductor pattern,
wherein the first inner electrode structure includes:
a first inner electrode that is a first portion of the gate electrode interposed between the substrate and the first semiconductor pattern,
a first barrier insulating pattern between the first inner electrode and the first source/drain pattern; and
a second barrier insulating pattern between the first inner electrode and the second source/drain pattern,
wherein the second inner electrode structure includes:
a second inner electrode that is a second portion of the gate electrode interposed between the first semiconductor pattern and the second semiconductor pattern,
a third barrier insulating pattern between the second inner electrode and the first source/drain pattern; and
a fourth barrier insulating pattern between the second inner electrode and the second source/drain pattern,
wherein an upper portion of the first inner electrode structure has a first width,
wherein a lower portion of the first inner electrode structure has a second width,
wherein an upper portion of the second inner electrode structure has a third width,
wherein a lower portion of the second inner electrode structure has a fourth width,
wherein a difference between the first width and the second width is greater than a difference between the third width and the fourth width.
18. The semiconductor device of claim 17 , wherein the second width is greater than the first width.
19. The semiconductor device of claim 17 , wherein the first inner electrode structure further includes a first gate dielectric pattern surrounding the first inner electrode and being between the first and second barrier insulating patterns, and
wherein the second inner electrode structure further includes a second gate dielectric pattern surrounding the second inner electrode and being between the third and fourth barrier insulating patterns.
20. The semiconductor device of claim 17 , wherein each of the first and second source/drain patterns includes an n-type impurity region.