IP Library Granted Patent US 12,300,754
Granted Patent B2
US 12,300,754 · App. 18/190,754 · Granted May 13, 2025

Channel configurations with stacked segments for gate-all-around based devices and methods of fabrication thereof

Inventors: Chih-Ching Wang (Kinmen County, TW); Jon-Hsu Ho (New Taipei, TW); Wen-Hsing Hsieh (Hsinchu, TW); Kuan-Lun Cheng (Hsin-Chu, TW); Zhiqiang Wu (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
H01L29/78696H01L29/42392
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Quick Facts
Patent No.
US 12,300,754
App. No.
18/190,754
Granted
May 13, 2025
Kind
B2
Abstract

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

Claims (57)

1. A method comprising:

forming a channel layer over a substrate, wherein the channel layer includes a first semiconductor material and a second semiconductor material, and the channel layer has:

a first horizontal segment extending along a first direction, the first horizontal segment having a first bulk portion formed from the first semiconductor material and a second bulk portion formed from the second semiconductor material, wherein the second bulk portion is laterally adjacent to the first bulk portion along the first direction,

a second horizontal segment extending along the first direction, the second horizontal segment having a third bulk portion formed from the first semiconductor material and a fourth bulk portion formed from the second semiconductor material, wherein the third bulk portion is laterally adjacent to the fourth bulk portion along the first direction, the first bulk portion is disposed over the third bulk portion along a second direction, the second bulk portion is disposed over the fourth bulk portion along the second direction, and the second direction is different than the first direction, and

a vertical segment having a fifth bulk portion formed from the second semiconductor material, wherein the vertical segment extends along the second direction and the fifth bulk portion is connected to the second bulk portion of the first horizontal segment and the fourth bulk portion of the second horizontal segment, and wherein the vertical segment has a width along the first direction, the vertical segment has a thickness along the second direction, and the thickness is greater than the width;

forming a gate stack that wraps the channel layer; and

forming a first source/drain and a second source/drain, wherein the channel layer extends between the first source/drain and the second source/drain.

2. The method of claim 1 , wherein a gap is between the first horizontal segment and the second horizontal segment along the second direction, and the gate stack fills the gap.

3. The method of claim 1 , wherein the forming the channel layer includes configuring and processing a semiconductor layer stack such that the first horizontal segment and the vertical segment form a first T-channel and the second horizontal segment forms a portion of a second T-channel, wherein the first T-channel is over the second T-channel.

4. The method of claim 3 , wherein:

the vertical segment is a first vertical segment;

the channel layer further includes a second vertical segment that extends between and connects the second horizontal segment to the substrate; and

the forming the channel layer includes configuring and processing the semiconductor layer stack such that the second vertical segment and the second horizontal segment form the second T-channel.

5. The method of claim 1 , wherein the forming the channel layer includes configuring and processing a semiconductor layer stack such that the first horizontal segment, the second horizontal segment, and the vertical segment form an H-shaped channel that is suspended above and separated from the substrate.

6. The method of claim 5 , wherein the channel layer is a first channel layer, and the method further includes forming a second channel layer between the H-shaped channel and the substrate, wherein the second channel layer includes a third horizontal segment that is suspended above and separated from the substrate.

7. The method of claim 1 , wherein:

the vertical segment is a first vertical segment;

the forming the channel layer includes configuring and processing a semiconductor layer stack such that the first horizontal segment, the second horizontal segment, and the first vertical segment form an H-shaped channel; and

the channel layer further includes a second vertical segment that extends between and connects the second horizontal segment to the substrate.

8. The method of claim 7 , wherein:

the channel layer is a first channel layer;

the method further includes forming a second channel layer, wherein the H-shaped channel is disposed vertically between the second channel layer and the substrate; and

the second channel layer includes a third horizontal segment that is suspended above and separated from the substrate.

9. The method of claim 1 , wherein:

the vertical segment is a first vertical segment;

the channel layer further includes a third horizontal segment and a second vertical segment, wherein the second vertical segment extends between and connects the second horizontal segment and the third horizontal segment; and

the forming the channel layer includes configuring and processing a semiconductor layer stack such that the first horizontal segment, the second horizontal segment, the third horizontal segment, the first vertical segment, and the second vertical segment form an E-shaped channel.

10. The method of claim 9 , wherein the channel layer further includes a third vertical segment that extends between and connects the third horizontal segment to the substrate.

11. A method comprising:

forming a channel over a substrate, wherein the channel includes a first nanosheet that includes a first semiconductor material and a second semiconductor material, a second nanosheet that includes the first semiconductor material and the second semiconductor material, and a nanosheet connecting portion that includes the second semiconductor material and connects the first nanosheet and the second nanosheet, wherein:

a distance is between the first nanosheet and the second nanosheet along a first direction that is substantially perpendicular to the substrate,

the nanosheet connecting portion has a thickness along a second direction that is different than the first direction, and

the thickness is less than the distance;

forming a first source/drain feature and a second source/drain feature over the substrate, wherein the first nanosheet and the second nanosheet extend from the first source/drain feature and the second source/drain feature along a third direction, wherein the third direction is different than the first direction and the second direction; and

forming a gate stack that wraps the channel, wherein the gate stack is disposed between the first source/drain feature and the second source/drain feature.

12. The method of claim 11 , wherein the forming the channel includes configuring and processing a semiconductor layer stack such that the channel is connected to the substrate.

13. The method of claim 11 , wherein the forming the channel includes configuring and processing a semiconductor layer stack such that the channel is not connected to the substrate.

14. The method of claim 11 , wherein the forming the channel includes configuring and processing a semiconductor layer stack such that the nanosheet connecting portion connects a first center of the first nanosheet with a second center of the second nanosheet.

15. The method of claim 11 , wherein the forming the channel includes configuring and processing a semiconductor layer stack such that the nanosheet connecting portion connects a first edge of the first nanosheet with a second edge of the second nanosheet.

16. The method of claim 11 , wherein the channel further includes a third nanosheet that is not connected to the first nanosheet and the second nanosheet.

17. A device comprising:

a channel layer over a substrate, wherein the channel layer includes a first semiconductor material and a second semiconductor material, and the channel layer has:

a first horizontal segment formed from the first semiconductor material and the second semiconductor material,

a second horizontal segment formed from the first semiconductor material and the second semiconductor material, wherein the first horizontal segment and the second horizontal segment extend along a first horizontal direction,

a vertical segment formed from the second semiconductor material, wherein the vertical segment extends between and connects a first portion of the first horizontal segment and a first portion of the second horizontal segment and a gap is between a second portion of the first horizontal segment and a second portion of the second horizontal segment, and

a third horizontal segment formed from the first semiconductor material, wherein the third horizontal segment is not connected to the first horizontal segment, the second horizontal segment, and the vertical segment;

a first source/drain feature and a second source/drain feature over the substrate, wherein the channel layer extends along a second horizontal direction from the first source/drain feature to the second source/drain feature, the second horizontal direction is different than the first horizontal direction, and the channel layer is connected to the first source/drain feature and the second source/drain feature; and

a gate stack that wraps the channel layer, wherein the gate stack fills the gap between the second portion of the first horizontal segment and the second portion of the second horizontal segment and the gate stack is between the first source/drain feature and the second source/drain feature along the second horizontal direction.

18. The device of claim 17 , wherein:

the first horizontal segment and the second horizontal segment each include a respective middle portion disposed between respective end portions, wherein the middle portion of the first horizontal segment is the first portion of the first horizontal segment, the middle portion of the second horizontal segment is the first portion of the second horizontal segment, the end portions of the first horizontal segment are the second portion of the first horizontal segment, and the end portions of the second horizontal segment are the second portion of the second horizontal segment; and

the middle portions are formed from the second semiconductor material, the end portions are formed from the first semiconductor material, and the vertical segment is connected to the middle portion of the first horizontal segment and the middle portion of the second horizontal segment.

19. The device of claim 17 , wherein:

the first portions of the first horizontal segment and the second horizontal segment are formed from the second semiconductor material;

the second portions of the first horizontal segment and the second horizontal segment are formed from the first semiconductor material;

the vertical segment, the first portion of the first horizontal segment, and the first portion of the second horizontal segment form a first side of the channel layer; and

the second portion of the first horizontal segment and the second portion of the second horizontal segment form a second side of the channel layer, wherein the first side of the channel layer is adjacent to and extends from the second side of the channel layer.

20. The device of claim 17 , wherein the third horizontal segment is between the second horizontal segment and the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2023
From: WANG, CHIH-CHING; HO, JON-HSU; CHENG, KUAN-LUN; HSIEH, WEN-HSING; WU, ZHIQIANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
Reel/Frame 063153/0385 →
Continuity (3)
Continuation 17206646 · Mar 19, 2021
Provisional Application 63030044 · May 26, 2020
Related Publication 20230327025A1 · Oct 12, 2023
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