Isolated gate driver
An isolated gate driver includes a transformer including primary and secondary windings, a synchronous rectifier connected between the secondary winding and an output terminal of the isolated gate driver, a first switch including a first terminal connected to a supply voltage, a second switch including a first terminal connected to the supply voltage, a first damping resistance connected between a first terminal of the secondary winding and a second terminal of the first switch, a second damping resistance connected between a second terminal of the secondary winding and a second terminal of the second switch, a first inverter including an input connected to the first terminal of the secondary winding and an output connected to a gate terminal of the first switch, and a second inverter including an input connected to the second terminal of the secondary winding and an output connected to a gate terminal of the second switch.
1. An isolated gate driver comprising:
a transformer including a primary winding and a secondary winding;
a synchronous rectifier electrically connected between the secondary winding and an output terminal of the isolated gate driver;
a first switch including a first terminal electrically connected to a supply voltage;
a second switch including a first terminal electrically connected to the supply voltage;
a first damping resistance electrically connected between a first terminal of the secondary winding and a second terminal of the first switch;
a second damping resistance electrically connected between a second terminal of the secondary winding and a second terminal of the second switch;
a first inverter including an input electrically connected to the first terminal of the secondary winding and an output electrically connected to a gate terminal of the first switch; and
a second inverter including an input electrically connected to the second terminal of the secondary winding and an output electrically connected to a gate terminal of the second switch.
2. The isolated gate driver according to claim 1 , further comprising:
a first buffer electrically connected to the first terminal of the secondary winding; and
a second buffer electrically connected to the second terminal of the secondary winding.
3. The isolated gate driver according to claim 1 , further comprising:
a first filter circuit that electrically connects the first terminal of the secondary winding to a first buffer; and
a second filter circuit that electrically connects the second terminal of the secondary winding to a second buffer.
4. The isolated gate driver according to claim 3 , wherein:
the first filter circuit includes:
a first filtering resistance electrically connected in series between the first terminal of the secondary winding and an input of the first buffer; and
a first filtering capacitance electrically connected between the input of the first buffer and the supply voltage, and
the second filter circuit includes:
a second filtering resistance electrically connected in series between the second terminal of the secondary winding and an input of the second buffer; and
a second filtering capacitance electrically connected between the input of the second buffer and the supply voltage.
5. The isolated gate driver according to claim 3 , wherein:
the first filter circuit includes a first delay cell, a first AND-gate, and the first buffer;
the first delay cell is electrically connected in series between the first terminal of the secondary winding and a first input of the first AND-gate;
a second input of the first AND-gate is electrically connected to the first terminal of the secondary winding;
an output of the first AND-gate is electrically connected to the first buffer;
the second filter circuit includes a second delay cell, a second AND-gate, and the second buffer;
the second delay cell is electrically connected in series between the second terminal of the secondary winding and a first input of the first AND-gate;
a second input of the second AND-gate is electrically connected to the second terminal of the secondary winding; and
an output of the second AND-gate is electrically connected to the second buffer.
6. An isolated gate driver comprising:
a transformer including a primary winding and a secondary winding;
a synchronous rectifier that provides power at a power output terminal of the isolated gate driver by rectifying high and low voltages provided by a first terminal of the secondary winding and high and low voltages provided by a second terminal of the secondary winding;
a buffer circuit that provides data signals at signal output terminals of the isolated gate driver based on the high and low voltages provided by the first terminal of the secondary winding and based on the high and low voltages provided by the second terminal of the secondary winding; and
an adjustable-damping circuit that increases an amount of damping provided on the first terminal of the secondary winding when the first terminal of the secondary winding provides the low voltage and that increases an amount of damping provided on the second terminal of the secondary winding when the second terminal of the secondary winding provides the low voltage.
7. The isolated gate driver circuit according to claim 6 , wherein
the adjustable-damping circuit increases the amount of damping provided on the first terminal of the secondary winding by connecting the first terminal of the secondary winding to a supply voltage through a first damping resistance; and
the adjustable-damping circuit increases the amount of damping provided on the second terminal of the secondary winding by connecting the second terminal of the secondary winding to the supply voltage through a second damping resistance.
8. The isolated gate driver circuit according to claim 6 , wherein the adjustable-damping circuit includes:
a first switch including a first terminal electrically connected to a supply voltage;
a second switch including a first terminal electrically connected to the supply voltage;
a first damping resistance electrically connected between the first terminal of the secondary winding and a second terminal of the first switch;
a second damping resistance electrically connected between the second terminal of the secondary winding and a second terminal of the second switch;
a first inverter including an input electrically connected to the first terminal of the secondary winding and an output electrically connected to a gate terminal of the first switch; and
a second inverter including an input electrically connected to the second terminal of the secondary winding and an output electrically connected to a gate terminal of the second switch.
9. The isolated gate driver according to claim 6 , wherein the buffer circuit includes:
a first buffer electrically connected to the first terminal of the secondary winding; and
a second buffer electrically connected to the second terminal of the secondary winding.
10. The isolated gate driver according to claim 6 , further comprising a filter circuit connected between the secondary winding and the buffer circuit.
11. The isolated gate driver according to claim 10 , wherein the filter circuit includes:
a first filter circuit that electrically connects the first terminal of the secondary winding to a first buffer; and
a second filter circuit that electrically connects the second terminal of the secondary winding to a second buffer.
12. The isolated gate driver according to claim 11 , wherein:
the first filter circuit includes:
a first filtering resistance electrically connected in series between the first terminal of the secondary winding and an input of the first buffer; and
a first filtering capacitance electrically connected between the input of the first buffer and the supply voltage, and
the second filter circuit includes:
a second filtering resistance electrically connected in series between the second terminal of the secondary winding and an input of the second buffer; and
a second filtering capacitance electrically connected between the input of the second buffer and the supply voltage.
13. The isolated gate driver according to claim 11 , wherein:
the first filter circuit includes a first delay cell, a first AND-gate, and the first buffer;
the first delay cell is electrically connected in series between the first terminal of the secondary winding and a first input of the first AND-gate;
a second input of the first AND-gate is electrically connected to the first terminal of the secondary winding;
an output of the first AND-gate is electrically connected to the first buffer;
the second filter circuit includes a second delay cell, a second AND-gate, and the second buffer;
the second delay cell is electrically connected in series between the second terminal of the secondary winding and a first input of the first AND-gate;
a second input of the second AND-gate is electrically connected to the second terminal of the secondary winding; and
an output of the second AND-gate is electrically connected to the second buffer.