Methods and systems of utilizing analog to digital converter (ADC) for multiply-accumulator (MAC)

1. An analog to digital converter (ADC) for a multiply-accumulator (MAC) system comprising:

an ADC control that receives a V REF and generates a plurality of timing signals to an ADC, and wherein the plurality of timing signals comprises an S 1 signal, an S 3 signal, an S 4 signal, an ECO signal, a CLOCK signal, and a COUNTER<N:0> signal;

the ADC that comprises:

a pre-charge system comprising a sense capacitor that stores an integrated charge I MAC over a time T and develops voltage V MAC , and wherein the S 1 signal defines the pre-charge phase of the sense capacitor, wherein the sense capacitor is pre-charged to a higher reference voltage V REF before the discharge phase occurs by the I MAC current,

an isolation/circuit device, wherein the isolation/circuit device is controlled by signal S 3 , wherein a turned-on isolation device enables the sense capacitor C 1 pre-charge to occur though itself and enables a path for the I MAC current to discharge the sense capacitor C 1 , wherein during the pre-charge and charge accumulation phase isolation the sense capacitor C 1 is expected to be turned on, and wherein the isolation device isolates sense capacitor C 1 from the pre-charge system,

a device controlled by the signal S 4 , wherein the signal S 4 transitions from a logic high state to a logic low state which turns off device in order to start the resolution phase,

a sense node of the sense capacitor C 1 , wherein the sense node follows a GNDX constant ramp of the ADC control unit at a resolution phase such that when the S 3 is also in the logic low state the sense node is at a high impedance,

a comparator which compares the sense node voltage with V REF , can detect and generate an active low output when sense node of the sense capacitor C 1 ramps back to the V REF voltage during resolution phase,

a CMOS logic-based system that received the output of the comparator output, wherein an active high output transition of CMOS logic-based system comprises a detection event when the sense node of sense cap ramps back to V REF during the resolution phase, wherein the CMOS logic-based system detects an ADC output even if there is zero input to the ADC, and wherein the CMOS logic-based system ensures a specified ADC output when the input goes beyond a range instead of a random ADC output, and

a Master Slave Flip Flop that synchronizes an output of the CMOS logic-based system, and wherein the Master Slave Flip Flop generates a pulse with pulse-width sufficient to latch a counter data and produce the binary ADC output.

2. The ADC for MAC system of claim 1 , wherein the ADC control unit comprises a finite state machine (FSM) system.

3. The ADC for MAC system of claim 2 ,

wherein the FSM generates the plurality of timing signals using a continuous clock signal as an input and generates CLOCK op at a resolution phase to be used by the ADC.

4. The ADC for MAC system of claim 3 , wherein the FSM comprises an N bit counter whose output is the COUNTER<N:0> signal that is used in the ADC.

5. The ADC for MAC system of claim 4 , wherein the ADC control unit comprises a GNDX ramping system that ramps a net GNDX at the resolution phase.

6. The ADC for MAC system of claim 5 , wherein the GNDX ramping system uses a capacitor C 2 , and wherein one plate of the capacitor C 2 is connected to the V REF and an other plate of capacitor C 2 is ramped up with a constant slope defined by an I REF .

7. The ADC for MAC system of claim 6 , wherein the GNDX ramping system comprises a unity follower system that employs an operation-amplifier-based unity gain buffer.

8. The ADC for MAC system of claim 1 , wherein V MAC =(1/C)I MAC *T.

9. The ADC for MAC system of claim 1 ,

wherein the I MAC current is a syncing current which discharges a sense capacitor to develop the voltage V MAC , across it.

10. The ADC for MAC system of claim 1 ,

wherein the isolation device uses a nMOS-based circuit,

wherein during the pre-charge and charge accumulation phase isolation the sense capacitor C 1 is expected to be turned on with the S 3 signal at a high state, and

wherein when the S 3 signal is in a logic low state, the sense node in ADC is at a high impedance state.

11. The ADC of MAC system of claim 1 , wherein the device employs an nMOS transistor.

12. The ADC of MAC system of claim 1 , wherein the ADC employs D-Latch.

13. The ADC of MAC system of claim 1 , wherein the ADC generates a pulse that is used to latch the counter data generated by the control unit.

14. The ADC of MAC system of claim 1 , wherein the sense node of sense capacitor C 1 ramps up and a resolution is achieved by ramping a bottom plate sense capacitor C 1 while maintaining a same voltage across the sense capacitor C 1 .

15. The ADC of MAC system of claim 1 , wherein the COUNTER<N:0> signal drives a plurality of ADCs.

16. The ADC of MAC system of claim 1 , wherein an error due a variation in the sense capacitor C 1 with a voltage swing is neutralized by special connection of a reference capacitor C 2 to ensure a similar variation in a charge accumulation phase and a resolution phase.