Scan chains with multi-bit cells and methods for testing the same
View Patent ↗A circuit includes a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit. The circuit includes a second plural number (S) of multiplexers operatively coupled to the scan chain, wherein the S is determined as N M , where the M represents a diagnostic resolution. The multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages.
1. A circuit, comprising:
a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit;
a second plural number (S) of multiplexers operatively coupled to the scan chain, wherein the S is determined as
N
M
,
where the MV represents a diagnostic resolution;
wherein the multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages.
2. The circuit of claim 1 , wherein the M is a plural number.
3. The circuit of claim 1 , wherein a number of the subset of stages bypassed is equal to the M.
4. The circuit of claim 1 , wherein a number of combinations of the S control signals is equal to S+1.
5. The circuit of claim 1 , wherein a first one of the multiplexers has:
a first input connected to an output of a second one of the multiplexers;
a second input connected to an output of the corresponding subset of stages; and
an output connected to a first input of a third one of the multiplexers.
6. The circuit of claim 5 , wherein the second multiplexer, the first multiplexer, and the third multiplexer are connected in such an order along a direction from a scan input of the scan chain to a scan output of the scan chain.
7. The circuit of claim 6 , wherein when the control signal received by the first multiplexer is at a first logic state, the first multiplexer is configured to couple the output of the corresponding subset of stages to the first input of the third multiplexer.
8. The circuit of claim 7 , wherein when the control signal received by the first multiplexer is at a second logic state, the multiplexer is configured to couple the output of the second multiplexer to the first input of the third multiplexer.
9. The circuit of claim 8 , wherein the corresponding subset of stages are thus bypassed.
10. The circuit of claim 1 , wherein a defect location at any of the subsets of the stages is determined based at least on comparing a first data pattern and a second data pattern, wherein the first data pattern and the second data pattern are unloaded by the scan chain based on a first combination of the control signals and a second combination of the control signals, respectively.
11. The circuit of claim 10 , wherein the first combination of the control signals and the second combination of the control signals are different from each other with only one bit.
12. A circuit, comprising:
a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit;
a second plural number (S) of multiplexers operatively coupled to the N stages, wherein the S is a factor of the N,
wherein the multiplexers are each configured to receive a respective one of control signals to selectively bypass a corresponding one of subsets of the stages.
13. The circuit of claim 12 , wherein the S is determined as
N
M
,
where the M represents a diagnostic resolution.
14. The circuit of claim 12 , wherein a first one, a second one, and a third one of the multiplexers are connected in such an order along a direction from a scan input of the scan chain to a scan output of the scan chain.
15. The circuit of claim 14 , wherein each of the multiplexers has:
a first input;
a second input; and
an output;
wherein the first input of the first multiplexer is coupled to the scan input, the second input of the first multiplexer is connected to an output of a first subset of the stages, and the output of the first multiplexer is connected to the first input of the second multiplexer;
wherein the second input of the second multiplexer is connected to an output of a second subset of the stages, and the output of the second multiplexer is connected to the first input of the third multiplexer; and
wherein the second input of the third multiplexer is connected to an output of a third subset of the stages, and the output of the third multiplexer is coupled to the scan output.
16. The circuit of claim 12 , wherein a number of combinations of the control signals received by the multiplexers is equal to S+1.
17. The circuit of claim 12 , a defect location at any of the subsets of the stages is determined based at least on comparing a first data pattern and a second data pattern, wherein the first data pattern and the second data pattern are unloaded by the scan chain based on a first combination of the control signals and a second combination of the control signals, respectively.
18. The circuit of claim 17 , wherein the first combination of the control signals and the second combination of the control signals are different from each other with only one bit.
19. A method for testing a scan chain, comprising:
providing a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit;
determining a diagnostic resolution (M);
generating a second plural number (P) of chain test patterns, wherein each of the chain test patterns is configured to bypass one or more subsets of the stages; and
determining a defect location at any subset of the stages based at least on comparing a first unloaded data pattern and a second unloaded data pattern generated by a first one of the chain test patterns and a second one of the chain test patterns, respectively;
wherein the P is determined as S+1, in which the S is determined as
N
M
.
20. The method of claim 19 , wherein the first chain test patterns and the second chain test patterns are different from each other with only one bit.