Granted Patent B2

US 12,307,181 · App. 17/871,456 · Granted May 20, 2025

Inventors: Glen Sescila (Austin, TX); Srikrishna Ramaswamy (Austin, TX)

Assignee: DELL PRODUCTS L.P.

G06F30/347

Abstract

Claims (74)

1. A method for offloading data operations to a field programmable gate array (FPGA), comprising:

loading, by the FPGA, a descriptor ring;

performing a first lookup, in the descriptor ring, to identify a first descriptor entry;

identifying, in the first descriptor entry, a first data operation;

making a first determination that the first data operation is unavailable in any of a plurality of module slots of the FPGA; and

based on the first determination:

loading a first operation module, matching the first data operation, into a first swappable module slot of the plurality of module slots;

steering first data, associated with the first descriptor entry, to the first swappable module slot for processing;

performing a second lookup, in the descriptor ring, to identify a second descriptor entry;

identifying, in the second descriptor entry, a second data operation, wherein the second data operation is the same as the first data operation;

making a second determination that the second data operation is available in the first swappable module slot;

based on the second determination:

steering second data, associated with the second descriptor entry, to the first swappable module slot for processing.

2. The method of claim 1 , wherein loading the first operation module into the first swappable module slot, comprises:

identifying, in a module library of the FPGA, the first operation module;

identifying the first swappable module slot; and

writing a configuration, associated with the first operation module, to the first swappable module slot.

3. The method of claim 2 , wherein identifying the first operation module, comprises:

comparing the first data operation against a plurality of operation modules in the module library, wherein the plurality of operation modules comprises the first operation module.

4. The method of claim 2 , wherein identifying the first swappable module slot, comprises:

identifying a second data operation, in the descriptor ring, that is going to be used after a plurality of other data operations in the descriptor ring are going to be used; and

identifying a second swappable module slot that comprises a second operation module associated with the second data operation.

5. The method of claim 2 , wherein after writing the configuration to the first swappable module slot, the method further comprises:

updating a module slot tracker, of the FPGA, to indicate that the first swappable module slot is loaded with the first operation module.

6. The method of claim 5 , wherein making the first determination that the first data operation is unavailable in any of the plurality of module slots, comprises:

performing a third lookup, in the module slot tracker, and failing to identify the first operation module.

7. The method of claim 1 , wherein after steering the first data to the first swappable module slot, the method further comprises:

making a third determination that the first swappable module slot is not idle; and

based on the third determination:

loading the first operation module into a second swappable module slot of the plurality of module slots; and

steering the second data, associated with the second descriptor entry, to the second swappable module slot for processing.

8. A non-transitory computer readable medium comprising instructions which, when executed by a field programmable gate array (FPGA), enables the FPGA to perform a method for offloading data operations to the FPGA, comprising:

loading, by the FPGA, a descriptor ring;

performing a first lookup, in the descriptor ring, to identify a first descriptor entry;

identifying, in the first descriptor entry, a first data operation;

making a first determination that the first data operation is unavailable in any of a plurality of module slots of the FPGA; and

based on the first determination:

loading a first operation module, matching the first data operation, into a first swappable module slot of the plurality of module slots;

steering first data, associated with the first descriptor entry, to the first swappable module slot for processing;

performing a second lookup, in the descriptor ring, to identify a second descriptor entry;

identifying, in the second descriptor entry, a second data operation, wherein the second data operation is the same as the first data operation;

making a second determination that the second data operation is available in the first swappable module slot;

based on the second determination:

making a third determination that the first swappable module slot is not idle;

based on the third determination:

loading the first operation module into a second swappable module slot of the plurality of module slots; and

steering second data, associated with the second descriptor entry, to the second swappable module slot for processing.

9. The non-transitory computer readable medium of claim 8 , wherein after steering the first data to the first swappable module slot, the method further comprises:

steering the second data, associated with the second descriptor entry, to the first swappable module slot for processing.

10. The non-transitory computer readable medium of claim 8 , wherein loading the first operation module into the first swappable module slot, comprises:

identifying, in a module library of the FPGA, the first operation module;

identifying the first swappable module slot; and

writing a configuration, associated with the first operation module, to the first swappable module slot.

11. The non-transitory computer readable medium of claim 10 , wherein identifying the first operation module, comprises:

comparing the first data operation against a plurality of operation modules in the module library, wherein the plurality of operation modules comprises the first operation module.

12. The non-transitory computer readable medium of claim 10 , wherein identifying the first swappable module slot, comprises:

identifying a second data operation, in the descriptor ring, that is going to be used after a plurality of other data operations in the descriptor ring are going to be used; and

identifying a second swappable module slot that comprises a second operation module associated with the second data operation.

13. The non-transitory computer readable medium of claim 10 , wherein after writing the configuration to the first swappable module slot, the method further comprises:

updating a module slot tracker, of the FPGA, to indicate that the first swappable module slot is loaded with the first operation module.

14. The non-transitory computer readable medium of claim 13 , wherein making the first determination that the first data operation is unavailable in any of the plurality of module slots, comprises:

performing a third lookup, in the module slot tracker, and failing to identify the first operation module.

15. A field programmable gate array (FPGA) configured to perform a method for offloading data operations, comprising:

loading a descriptor ring;

performing a first lookup, in the descriptor ring, to identify a first descriptor entry;

identifying, in the first descriptor entry, a first data operation;

making a first determination that the first data operation is unavailable in any of a plurality of module slots of the FPGA; and

based on the first determination:

loading a first operation module, matching the first data operation, into a first swappable module slot of the plurality of module slots, comprises:

identifying, in a module library of the FPGA, the first operation module;

identifying the first swappable module slot; and

writing a configuration, associated with the first operation module, to the first swappable module slot.

16. The FPGA of claim 15 , wherein after loading the first operation module into the first swappable module slot, the method further comprises:

steering first data, associated with the first descriptor entry, to the first swappable module slot for processing.

Assignments (1)

Continuity (1)

References Cited (11)