Enhanced gradient seeding scheme during a program operation in a memory sub-system
Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a first positive voltage to be applied to a first plurality of word lines of a data block of the memory array during a seeding phase of a program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation;
causing a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage; and
causing a third positive voltage to be applied to one or more third word lines coupled to one or more third memory cells on the source-side of the one or more second memory cells in the string of memory cells during the seeding phase, wherein the third positive voltage is less than the second positive voltage.
2. The memory device of claim 1 , wherein the control logic is to perform operations further comprising:
causing a ground voltage to be applied to a second plurality of word lines of the data block during the seeding phase, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string, wherein the second plurality of memory cells are adjacent to the one or more third memory cells on the source-side of the string of memory cells.
3. The memory device of claim 1 , wherein the selected word line is coupled to a first memory cell of the first plurality of memory cells, and wherein causing the first positive voltage to be applied to the first plurality of word lines of the data block comprises:
causing the first positive voltage to be applied to one or more fourth word lines of the first plurality of word lines coupled to one or more of the first plurality of memory cells on a drain-side of the first memory cell in the string of memory cells.
4. The memory device of claim 3 , wherein causing the first positive voltage to be applied to the first plurality of word lines of the data block comprises:
causing the first positive voltage to be applied to one or more fifth word lines of the first plurality of word lines coupled to one or more of the first plurality of memory cells on a source-side of the first memory cell in the string of memory cells.
5. The memory device of claim 4 , wherein the control logic is to perform operations further comprising:
causing respective biasing voltages to be applied to word lines coupled to a select gate device and one or more inactive memory cells on a drain-side of the first plurality of memory cells in the string of memory cells during the seeding phase.
6. The memory device of claim 5 , wherein the control logic is to perform operations further comprising:
causing the first positive voltage applied to the selected word line and applied to the one or more fourth word lines to ramp down to an intermediate voltage at an end of the seeding phase, wherein the intermediate voltage is less than the first positive voltage and greater than a ground voltage; and
causing the first positive voltage applied to the one or more fifth word lines, the second positive voltage applied to the one or more second word lines, and the third positive voltage applied to the one or more third word lines to ramp down to the ground voltage at the end of the seeding phase.
7. The memory device of claim 6 , wherein the control logic is to perform operations further comprising:
causing the respective biasing voltages applied to the word lines coupled to the select gate device and the one or more inactive memory cells to ramp down to the ground voltage after a delay period at the end of the seeding phase, wherein the delay period comprises a period of time after the first positive voltage, the second positive voltage, and the third positive voltage have been ramped down to at least one of the intermediate voltage or the ground voltage.
8. A method comprising:
causing a first positive voltage to be applied to a first plurality of word lines of a data block of a memory array of a memory device during a seeding phase of a program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation;
causing a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage; and
causing a third positive voltage to be applied to one or more third word lines coupled to one or more third memory cells on the source-side of the one or more second memory cells in the string of memory cells during the seeding phase, wherein the third positive voltage is less than the second positive voltage.
9. The method of claim 8 , further comprising:
causing a ground voltage to be applied to a second plurality of word lines of the data block during the seeding phase, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string, wherein the second plurality of memory cells are adjacent to the one or more third memory cells on the source-side of the string of memory cells.
10. The method of claim 8 , wherein the selected word line is coupled to a first memory cell of the first plurality of memory cells, and wherein causing the first positive voltage to be applied to the first plurality of word lines of the data block comprises:
causing the first positive voltage to be applied to one or more fourth word lines of the first plurality of word lines coupled to one or more of the first plurality of memory cells on a drain-side of the first memory cell in the string of memory cells.
11. The method of claim 10 , wherein causing the first positive voltage to be applied to the first plurality of word lines of the data block comprises:
causing the first positive voltage to be applied to one or more fifth word lines of the first plurality of word lines coupled to one or more of the first plurality of memory cells on a source-side of the first memory cell in the string of memory cells.
12. The method of claim 11 , further comprising:
causing respective biasing voltages to be applied to word lines coupled to a select gate device and one or more inactive memory cells on a drain-side of the first plurality of memory cells in the string of memory cells during the seeding phase.
13. The method of claim 12 , further comprising:
causing the first positive voltage applied to the selected word line and applied to the one or more fourth word lines to ramp down to an intermediate voltage at an end of the seeding phase, wherein the intermediate voltage is less than the first positive voltage and greater than a ground voltage; and
causing the first positive voltage applied to the one or more fifth word lines, the second positive voltage applied to the one or more second word lines, and the third positive voltage applied to the one or more third word lines to ramp down to the ground voltage at the end of the seeding phase.
14. The method of claim 13 , further comprising:
causing the respective biasing voltages applied to the word lines coupled to the select gate device and the one or more inactive memory cells to ramp down to the ground voltage after a delay period at the end of the seeding phase, wherein the delay period comprises a period of time after the first positive voltage, the second positive voltage, and the third positive voltage have been ramped down to at least one of the intermediate voltage or the ground voltage.
15. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
causing a first positive voltage to be applied to a selected word line of a segment of the memory array during a seeding phase of a program operation, wherein the selected word line is coupled to a corresponding memory cell in a string of memory cells;
causing a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the corresponding memory cell in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage; and
causing a third positive voltage to be applied to one or more third word lines coupled to one or more third memory cells on the source-side of the one or more second memory cells in the string of memory cells during the seeding phase, wherein the third positive voltage is less than the second positive voltage.
16. The memory device of claim 15 , wherein the control logic is to perform operations further comprising:
causing a ground voltage to be applied to a second plurality of word lines of the segment during the seeding phase, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string, wherein the second plurality of memory cells are adjacent to the one or more third memory cells on the source-side of the string of memory cells.
17. The memory device of claim 15 , wherein the control logic is to perform operations further comprising:
causing the first positive voltage to be applied to one or more fourth word lines coupled to one or more memory cells in the string of memory cells on a drain-side of the corresponding memory cell in the string of memory cells.
18. The memory device of claim 17 , wherein the control logic is to perform operations further comprising:
causing the first positive voltage to be applied to one or more fifth word lines coupled to one or more memory cells in the string of memory cells on a source-side of the corresponding memory cell in the string of memory cells.
19. The memory device of claim 18 , wherein the control logic is to perform operations further comprising:
causing respective biasing voltages to be applied to word lines coupled to a select gate device and one or more inactive memory cells on a drain-side of the corresponding memory cell in the string of memory cells during the seeding phase.
20. The memory device of claim 19 , wherein the control logic is to perform operations further comprising:
causing the first positive voltage applied to the selected word line and applied to the one or more fourth word lines to ramp down to an intermediate voltage at an end of the seeding phase, wherein the intermediate voltage is less than the first positive voltage and greater than a ground voltage; and
causing the first positive voltage applied to the one or more fifth word lines, the second positive voltage applied to the one or more second word lines, and the third positive voltage applied to the one or more third word lines to ramp down to the ground voltage at the end of the seeding phase.