Granted Patent B2

US 12,308,148 · App. 17/978,907 · Granted May 20, 2025

Inventor: Yoshiaki Toyoda (Nagano, JP)

Assignee: FUJI ELECTRIC CO., LTD.

H01C7/06H01C7/021H01C7/022H01C7/041H01C7/042

Abstract

Claims (25)

1. A semiconductor device, comprising:

a polysilicon layer;

a resistance region provided in the polysilicon layer;

a first contact region provided in the resistance region, the first contact region having the same conductivity type as the resistance region and having a higher impurity concentration than the resistance region;

a first wiring electrically connected to one end of the resistance region via a plurality of first vias; and

a second wiring electrically connected to the other end of the resistance region via a plurality of second vias,

wherein at least one of the plurality of first vias and the plurality of second vias is in contact with the first contact region so as to form a low resistance contact structure with respect to the resistance region, and

wherein at least another one of the plurality of first vias and the plurality of second vias forms a high resistance contact structure with respect to the resistance region that has a contact resistance higher than a contact resistance of the low resistance contact structure.

2. The semiconductor device according to claim 1 , wherein at least one of the contact resistance of the low resistance contact structure, the contact resistance of the high resistance contact structure, and a sheet resistance of the resistance region has a temperature coefficient that has a plus or negative sign opposite to a temperature coefficient of at least another one of the contact resistance of the low resistance contact structure, the contact resistance of the high resistance contact structure, and the sheet resistance of the resistance region.

3. The semiconductor device according to claim 1 , wherein the contact resistance of the low resistance contact structure has a positive temperature coefficient, the contact resistance of the high resistance contact structure has a negative temperature coefficient, and a sheet resistance of the resistance region has a positive temperature coefficient.

4. The semiconductor device according to claim 1 , wherein a number of the low resistance contact structure, a number of the high resistance contact structures, and lateral dimensions of the resistance region are such that a temperature coefficient of an entire resistance of a resistor composed of the low resistance contact structure, the high resistance contact structure, and the resistance region is substantially zero.

5. The semiconductor device according to claim 1 , wherein said at least another one of the plurality of first vias and the plurality of second vias is directly in contact with the resistance region to form the high resistance contact structure.

6. The semiconductor device according to claim 1 , further comprising a second contact region in the resistance region, the second contact region having the same conductivity type as the resistance region and having a lower impurity concentration than the resistance region,

wherein said at least another one of the plurality of first vias and the plurality of second vias is in contact with the second contact region so as to form the high resistance contact structure with respect to the resistance region.

7. The semiconductor device according to claim 1 , further comprising a second contact region in the resistance region, the second contact region having the same conductivity type as the resistance region and having an impurity concentration that is higher than an impurity concentration of the resistance region and that is lower than the impurity concentration of the first contact region,

wherein said at least another one of the plurality of first vias and the plurality of second vias is in contact with the second contact region so as to form the high resistance contact structure with respect to the resistance region.

8. The semiconductor device according to claim 1 , further comprising a second contact region in the resistance region, the second contact region having the same conductivity type as the resistance region and having a lower impurity concentration than the resistance region,

wherein said at least another one of the plurality of first vias and the plurality of second vias is in contact with the second contact region so as to form the high resistance contact structure with respect to the resistance region, and

wherein still another one of the plurality of first vias and the plurality of second vias is directly in contact with the resistance region so as to form a middle resistance contact structure with respect to the resistance region that has a contact resistance between the contact resistance of the high resistance contact structure and the contact resistance of the low resistance contact structure.

9. The semiconductor device according to claim 1 ,

wherein said at least one of the plurality of first vias and the plurality of second vias constituting the low resistance contact structure is one or more of the plurality of first vias, and

wherein said at least another one of the plurality of first vias and the plurality of second vias constituting the high resistance contact structure is another one or more of the plurality of first vias.

10. The semiconductor device according to claim 9 ,

wherein the plurality of second vias have the same configuration as the plurality of first vias, and the plurality of first vias and the plurality of second vias are arranged line symmetrically with respect to each other.

11. The semiconductor device according to claim 1 , wherein said resistance region is a p-type diffusion region.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (17)