IP Library Granted Patent US 12,308,175
Granted Patent B2
US 12,308,175 · App. 17/479,051 · Granted May 20, 2025

Multilayer ceramic capacitor

Inventors: Togo Matsui (Nagaokakyo, JP); Yukito Nishimura (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01G4/30H01G4/008H01G4/012H01G4/1218
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Quick Facts
Patent No.
US 12,308,175
App. No.
17/479,051
Granted
May 20, 2025
Kind
B2
Abstract

A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrodes alternately laminated therein, and external electrodes respectively on a first end surface and a second end surface of the multilayer body in a length direction intersecting a lamination direction. The internal electrodes each include an opposing portion, a thick portion extending from the opposing portion to one of the first end surface or the second end surface and coupled to one of the external electrodes, and is thicker than the opposing portion in the lamination direction, and a thin portion extending from the opposing portion to another of the first end surface or the second end surface and uncoupled with the external electrodes, and is thinner than the opposing portion in the lamination direction.

Claims (32)

1. A multilayer ceramic capacitor comprising:

a multilayer body including dielectric layers and internal electrodes alternately laminated therein; and

external electrodes respectively on a first end surface and a second end surface, which are respectively on both ends of the multilayer body in a length direction intersecting a lamination direction; wherein

each of the internal electrodes includes:

an opposing portion with a constant or substantially constant thickness;

a thick portion extending from the opposing portion to one of the first end surface or the second end surface and coupled to one of the external electrodes, and is thicker than the opposing portion in the lamination direction; and

a thin portion extending from the opposing portion to another of the first end surface or the second end surface and uncoupled with the external electrodes, and is thinner than the opposing portion in the lamination direction;

in adjacent internal electrodes in the lamination direction, the thin portion of one of the adjacent internal electrodes is opposed to the thick portion of another one of the adjacent internal electrodes;

an interval in the lamination direction between the thick portion and the thin portion facing each other is constant or substantially constant;

at least one surface of the thin portion extends parallel or substantially parallel to the length direction; and

a deviation amount in the lamination direction between ends of the internal electrodes in a width direction intersecting the lamination direction and the length direction is about 0.5 μm or less.

2. The multilayer ceramic capacitor according to claim 1 , wherein

a thickness of the thick portion increases in the lamination direction from the opposing portion toward the one of the first end surface or the second end surface; and

a thickness of the thin portion decreases in the lamination direction from the opposing portion toward the another of the first end surface or the second end surface.

3. The multilayer ceramic capacitor according to claim 1 , wherein dimensions of the thin portion and the thick portion in the length direction are about 5 μm to about 30 μm.

4. The multilayer ceramic capacitor according to claim 1 , wherein floating electrodes are interspersed between the thin portion and the another of the first end surface or the second end surface to which the thin portion extends.

5. The multilayer ceramic capacitor according to claim 1 , wherein the multilayer body has a rectangular or substantially rectangular shape.

6. The multilayer ceramic capacitor according to claim 1 , wherein the multilayer body has a dimension in the length direction of about 0.2 mm or more and about 10 mm or less, a dimension in a width direction of about 0.1 mm or more and about 10 mm or less, and a dimension in the lamination direction of about 0.1 mm or more and about 5 mm or less.

7. The multilayer ceramic capacitor according to claim 1 , wherein the multilayer body includes a laminate chip and a side gap portion.

8. The multilayer ceramic capacitor according to claim 7 , wherein

the laminate chip includes an inner layer portion and outer layer portions on each side of the inner layer portion in the lamination direction; and

the inner layer portion includes the dielectric layers and the internal electrodes.

9. The multilayer ceramic capacitor according to claim 1 , wherein each of the dielectric layers has a thickness of about 0.5 μm.

10. The multilayer ceramic capacitor according to claim 1 , wherein each of the dielectric layers includes a dielectric ceramic including BaTiO 3 as a main component.

11. The multilayer ceramic capacitor according to claim 10 , wherein each of the dielectric layers further includes at least one of a Mn compound, a Fe compound, a Cr compound, a Co compound, and a Ni compound as a sub-component.

12. The multilayer ceramic capacitor according to claim 8 , wherein the laminate chip includes 15 or more and 700 or less of the dielectric layers.

13. The multilayer ceramic capacitor according to claim 1 , wherein each of the internal electrodes includes at least one of Ni, Cu, Ag, Pd, Ag-Pd alloy, or Au.

14. The multilayer ceramic capacitor according to claim 1 , wherein a thickness of the opposing portion is about 0.5 μm or more and about 2.0 mm or less.

15. The multilayer ceramic capacitor according to claim 1 , wherein the thin portion has a curved shape.

16. The multilayer ceramic capacitor according to claim 1 , wherein the thick portion has a curved shape.

17. The multilayer ceramic capacitor according to claim 1 , wherein a maximum thickness of the thickness portion is about twice a thickness of the opposing portion.

18. The multilayer ceramic capacitor according to claim 1 , wherein at least one surface of the thick portion extends parallel or substantially parallel to the length direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2021
From: MATSUI, TOGO; NISHIMURA, YUKITO
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 057528/0376 →
Priority Claims (1)
JP 2020-160018 · Sep 24, 2020 · national
Continuity (1)
Related Publication 20220093340A1 · Mar 24, 2022
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