Controller of power conversion circuit and operating method thereof
A controller of a power conversion circuit, coupled to a smart power stage (SPS), controls SPS to convert an input voltage into an output voltage and provides an output current. The SPS provides a current monitoring signal to the controller. The controller includes a control loop, a sampling circuit and a current reconstruction circuit. The control loop is coupled to SPS and generates a pulse-width modulation (PWM) signal to control the operation of SPS. The sampling circuit is coupled to SPS and receives the current monitoring signal. The current monitoring signal is sampled according to PWM signal to obtain a calibration reference value. The current reconstruction circuit is coupled to the control loop and sampling circuit and generates a reconstructed current corresponding to actual output current. The reconstructed current is produced according to an input voltage, a reference voltage and PWM signal and calibrated using the calibration reference value.
1. A controller of a power conversion circuit, coupled to a smart power stage (SPS), configured to control the SPS to convert an input voltage into an output voltage and provide an output current, the SPS providing a current monitoring signal to the controller, the controller comprising:
a control loop, coupled to the SPS, configured to generate a pulse width modulation (PWM) signal according to the output voltage and a reference voltage to control an operation of the SPS;
a sampling circuit, coupled to the SPS, configured to receive the current monitoring signal and sample the current monitoring signal according to the PWM signal to obtain a calibration reference value; and
a current reconstruction circuit, coupled to the control loop and the sampling circuit, wherein the current reconstruction circuit configured to generate a reconstructed current corresponding to the current monitoring signal according to the input voltage, the reference voltage and the PWM signal and calibrate the reconstructed current by using the calibration reference value.
2. The controller of claim 1 , wherein the power conversion circuit has an output inductance; when the PWM signal is in a first state, the current reconstruction circuit generates a step-up value according to the following formula:
ISTU =[( VIN−VREF )/ SET]×TCLK,
wherein VIN is the input voltage, VREF is the reference voltage, SET is a setting value related to the output inductance, TCLK is a system clock and ISTU is the step-up value.
3. The controller of claim 1 , wherein the power conversion circuit has an output inductance; when the PWM signal is in a second state, the current reconstruction circuit generates a step-down value according to the following formula:
ISTD =( VREF/SET )× TCLK,
wherein VREF is the reference voltage, SET is a setting value related to the output inductance, TCLK is a system clock and ISTD is the step-down value.
4. The controller of claim 1 , wherein the current reconstruction circuit comprises:
a step value generator, coupled to the control loop, configured to generate a step value according to the input voltage, the reference voltage and the PWM signal;
a calibrator, coupled to the control loop, configured to generate a calibration value according to the calibration reference value and the reconstructed current at a rising edge of the PWM signal when the pulse width modulation signal is rising; and
a calculator, coupled to the step value generator and the calibrator respectively, configured to generate the reconstructed current according to the step value and the calibration value.
5. The controller of claim 4 , wherein the calibration value is generated according to the following formula:
IOFF=DIMON−IRE,
wherein DIMON is the calibration reference value, IOFF is the calibration value, and IRE is the reconstructed current.
6. The controller of claim 4 , wherein the reconstructed current is calibrated according to the following formula:
IRE′=IST+IOFF+IRE,
wherein IST is the step value, IOFF is the calibration value, IRE is the reconstructed current value of a first system clock, IRE′ is the reconstructed current value of a second system clock, and the second system clock is immediately after the first system clock.
7. The controller of claim 1 , wherein the sampling circuit also comprises a timer, when a cycle of the PWM signal obtained by the timer is less than a default time, the controller stops generating the calibration value.
8. A method of operating a controller of a power conversion circuit used to control a smart power stage (SPS) to convert an input voltage into an output voltage and provide an output current, the SPS providing a current monitoring signal related to the output current to the controller, the method comprising following steps of:
(a) generating a PWM signal according to the output voltage and a reference voltage to control the operation of the SPS;
(b) sampling the current monitoring signal according to the PWM signal to obtain a calibration reference value; and
(c) generating a reconstructed current corresponding to the current monitoring signal according to the input voltage, the reference voltage and the PWM signal and calibrating the reconstructed current by using the calibration reference value.
9. The method of claim 8 , wherein the power conversion circuit has an output inductance; the step (c) further comprises:
when the PWM signal is in a first state, generating a step-up value according to the following formula:
ISTU =[( VIN−VREF )/ SET]×TCLK,
wherein VIN is the input voltage, VREF is the reference voltage, SET is a setting value related to the output inductance, TCLK is a system clock and ISTU is the step-up value.
10. The method of claim 8 , wherein the power conversion circuit has an output inductance; the step (c) further comprises:
when the PWM signal is in a second state, generating a step-down value according to the following formula:
ISTD =( VREF/SET )× TCLK,
wherein VREF is the reference voltage, SET is a setting value related to the output inductance, TCLK is a system clock and ISTD is the step-down value.
11. The method of claim 8 , wherein the step (c) further comprises:
generating a step value according to the input voltage, the reference voltage and the PWM signal;
generating a calibration value according to the calibration reference value and the reconstructed current at a rising edge of the PWM signal when the pulse width modulation signal is rising; and
generating a reconstructed current according to the step value and the calibration value.
12. The method of claim 11 , wherein the calibration value is generated according to the following formula:
IOFF=DIMON−IRE,
wherein DIMON is the calibration reference value, IOFF is the calibration value, and IRE is the reconstructed current.
13. The method of claim 11 , wherein the reconstructed current is generated according to the following formula:
IRE′=IST+IOFF+IRE,
wherein IST is the step value, IOFF is the calibration value, IRE is the reconstructed current value of a first system clock, IRE′ is the reconstructed current value of a second system clock, and the second system clock is immediately after the first system clock.
14. The method of claim 11 , wherein the method further comprises:
when a cycle of the PWM signal is less than a default time, stopping generating the calibration value.