Ethernet pause aggregation for a relay device
A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.
1. A device comprising:
a processor;
memory in electronic communication with the processor; and
instructions stored in the memory, the instructions being executable by the processor to:
receive a control frame associated with transmitting data packets;
determine a state of a state machine based on the control frame;
transmit, when the state of the state machine is a first state, a pause request comprising the control frame to one or more of at least two other devices to pause a flow of data between the device and the one or more of the at least two other devices; and
enable the flow of data between the device and the one or more of the at least two other devices when the state of the state machine is a second state different than the first state, wherein the state of the state machine mirrors a state of one of the at least two other devices.
2. The device of claim 1 , wherein input bandwidth of the device is different than output bandwidth of the device.
3. The device of claim 1 , wherein input bandwidth of the device is greater than output bandwidth of the device.
4. The device of claim 1 , further comprising:
the state machine.
5. The device of claim 1 , further comprising:
a receive buffer that stores the data packets.
6. The device of claim 5 , wherein the memory includes instructions that are executable by the processor to:
determine a quantity of empty data byte locations within the receive buffer;
transmit the pause request to the one or more of the at least two other devices when the quantity of empty data byte locations is below a threshold; and
enable the flow of data between the device and the one or more of the at least two other devices when the quantity of empty data byte locations is above the threshold.
7. The device of claim 1 , wherein the data packets are secured with a security protocol.
8. The device of claim 7 , wherein the security protocol corresponds to Media Access Control Security (MACsec).
9. The device of claim 7 , wherein the security protocol corresponds to Internet Protocol security (IPsec).
10. A system comprising:
a host device;
a peer device; and
a relay device connected between the host device and the peer device, the relay device comprising:
a processor;
memory in electronic communication with the processor; and
instructions stored in the memory, the instructions being executable by the processor to:
receive a control frame associated with data packets;
determine a state of a state machine based on the control frame;
transmit, when the state of the state machine is a first state, a pause request comprising the control frame to the host device or the peer device to pause a flow of data between the host device and the peer device; and
enable the flow of data between the host device and the peer device when the state of the state machine is a second state different than the first state, wherein the state of the state machine mirrors a state of one of the host device or the peer device.
11. The system of claim 10 , wherein bandwidth of the relay device at a side connected to the host device is different than bandwidth of the relay device at a side connected to the peer device.
12. The system of claim 11 , wherein the bandwidth of the relay device at the side connected to the host device is greater than the bandwidth of the relay device at the side connected to the peer device.
13. The system of claim 10 , wherein the relay device further comprises the state machine.
14. The system of claim 10 , wherein the relay device further comprises:
a receive buffer that stores the data packets.
15. The system of claim 14 , wherein the memory includes instructions that are executable by the processor to:
determine a quantity of empty data byte locations within the receive buffer;
transmit the pause request to the host device or the peer device when the quantity of empty data byte locations is below a threshold; and
enable the flow of data between the host device and the peer device when the quantity of empty data byte locations is above the threshold.
16. The system of claim 10 , wherein the data packets are secured with a security protocol.
17. A device, comprising:
a processor;
memory in electronic communication with the processor; and
instructions stored in the memory, the instructions being executable by the processor to:
receive a control frame associated with data packets;
determine a state of a state machine based on the control frame;
transmit, when the state of the state machine is a first state, a pause request comprising the control frame to one or more of at least two other devices to pause a flow of data between the device and the one or more of the at least two other devices;
determine that the state of the state machine changes from the first state to a second state different than the first state; and
enable, in response to the first state changing to the second state, the flow of data between the device and the one or more of the at least two other devices, wherein the state of the state machine mirrors a state of the one or more of the at least two other devices.