Granted Patent B2

US 12,309,999 · App. 17/816,436 · Granted May 20, 2025

Inventors: Youming Liu (Hefei, CN); Deyuan Xiao (Hefei, CN)

Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.

H10B12/30H10B12/05H10B12/482H10B12/488

Abstract

Claims (58)

1. A semiconductor structure, comprising:

a substrate;

a memory cell array, located on the substrate, wherein the memory cell array comprises a plurality of transistor units, each of the transistor units comprises a first transistor and a second transistor extending along a first direction and electrically connected to each other, and the first direction is parallel to the substrate;

a first bit line, penetrating the memory cell array and electrically connected to the first transistor;

a second bit line, penetrating the memory cell array and electrically connected to the second transistor;

a first word line, electrically connected to the first transistor; and

a second word line, electrically connected to the second transistor.

2. The semiconductor structure according to claim 1 , wherein a plurality of first bit lines, a plurality of first word lines, a plurality of second bit lines, and a plurality of second word lines are provided;

the plurality of first word lines and the plurality of second word lines extend along a third direction and are electrically isolated from each other; and

the plurality of first bit lines and the plurality of second bit lines extend along a second direction and are electrically isolated from each other; and/or a first step is formed at an end of the plurality of first bit lines that is away from the memory cell array, and a second step is formed at an end of the plurality of second bit lines that is away from the memory cell array.

3. The semiconductor structure according to claim 2 , wherein the first step and the second step are located at a same side of the memory cell array.

4. The semiconductor structure according to claim 2 , wherein each of the first bit lines is electrically connected to a plurality of first transistors that are located in a same row along the second direction; and each of the first word lines is electrically connected to a plurality of first transistors that are located in a same column along the third direction; and

each of the second bit lines is electrically connected to a plurality of second transistors that are located in a same row along the second direction; and each of the second word lines is electrically connected to a plurality of second transistors that are located in a same column along the third direction.

5. The semiconductor structure according to claim 1 , wherein the first transistor and the second transistor each comprise:

a channel, in which an accommodation space is formed;

a gate, provided with a first terminal and a second terminal that are opposite to each other along the first direction, wherein the first terminal of the gate is located outside the accommodation space, and the second terminal of the gate is located in the accommodation space;

a dielectric layer, located between the gate and the channel and isolating the gate from the channel in an insulated manner;

a source, provided at one end of the channel; and

a drain, provided at the other end of the channel, wherein the drain and the source are arranged at an interval along the first direction.

6. The semiconductor structure according to claim 5 , wherein the channel comprises a top wall, a bottom wall, and a sidewall that define the accommodation space, the top wall is provided with an opening, and the second terminal of the gate is exposed outside the accommodation space via the opening; and

the source covers the bottom wall of the channel and covers a part of the sidewall close to the bottom wall, and the drain covers the top wall of the channel and covers a part of the sidewall close to the top wall.

7. The semiconductor structure according to claim 5 , wherein a material of the channel comprises one from the group consisting of indium gallium zinc oxide, polysilicon, monocrystalline silicon, silicon germanide and silicon carbide.

8. The semiconductor structure according to claim 5 , wherein the first bit line is electrically connected to the drain of the first transistor, and the first word line is electrically connected to the source of the first transistor;

the second bit line is electrically connected to the source of the second transistor, and the second word line is electrically connected to the gate of the second transistor; and

the gate of the first transistor is electrically connected to the drain of the second transistor.

9. The semiconductor structure according to claim 8 , wherein along the first direction, a first isolation layer is further provided between the second bit line and the second word line, to isolate the second bit line from the second word line in an insulated manner, and the second transistor penetrates the first isolation layer.

10. The semiconductor structure according to claim 1 , wherein the semiconductor structure further comprises a first bit line plug, a second bit line plug, a first word line plug, and a second word line plug that extend along a third direction; and

the first bit line plug is electrically connected to the first bit line, the second bit line plug is electrically connected to the second bit line, the first word line plug is electrically connected to the first word line, and the second word line plug is electrically connected to the second word line.

11. A manufacturing method of a semiconductor structure, comprising:

providing a substrate; and

forming a memory cell array, first bit lines, second bit lines, first word lines, and second word lines on the substrate;

wherein the memory cell array comprises a plurality of transistor units, each of the transistor units comprises a first transistor and a second transistor extending along a first direction and electrically connected to each other, and the first direction is parallel to the substrate; and

the first bit line penetrates the memory cell array and is electrically connected to the first transistor; the second bit line penetrates the memory cell array and is electrically connected to the second transistor; the first word line is electrically connected to the first transistor; and the second word line is electrically connected to the second transistor.

12. The manufacturing method according to claim 11 , wherein the forming a memory cell array, first bit lines, second bit lines, first word lines, and second word lines on the substrate comprises:

forming a first gate array and a second gate array that are arranged at an interval along the first direction on the substrate, wherein the first gate array comprises a plurality of first gates that are arranged at intervals along a second direction and arranged at intervals along a third direction, and the second gate array comprises a plurality of second gates that are arranged at intervals along the second direction and arranged at intervals along the third direction;

forming a dielectric layer on the first gate and the second gate, and forming a channel on the dielectric layer, wherein first terminals of the first gate and the second gate both extend to outsides of the corresponding channels;

forming a first metal layer and a second metal layer, wherein the first metal layer covers the channel located at a second terminal of the first gate, the second metal layer covers the channel close to the first terminal of the second gate, and the second terminal and the first terminal are opposite to each other along the first direction;

forming a first bit line and a second bit line that extend along the second direction, wherein the first bit line covers the first metal layer, and the second bit line covers the second metal layer;

forming a third metal layer and a fourth metal layer, wherein the third metal layer covers the channel close to the first terminal of the first gate, the fourth metal layer covers the channel at a second terminal of the second gate, the third metal layer and the first metal layer are spaced apart, the fourth metal layer and the second metal layer are spaced apart, and the fourth metal layer is in contact with the first terminal of the first gate; and

forming a first word line and a second word line that extend along the third direction, wherein the first word line covers the third metal layer, and the second word line covers the first terminal of the second gate.

13. The manufacturing method according to claim 12 , wherein the forming a first gate array and a second gate array that are spaced apart along the first direction on the substrate comprises:

forming a first laminated structure on the substrate, wherein the first laminated structure has a first region and a second region, and the first laminated structure comprises first sacrificial layers and initial gate layers that are arranged alternately along the third direction;

removing a part of the first laminated structure, to form a first trench that extends along the first direction in the first region, and form a second trench that extends along the second direction in the second region, wherein the first trench partitions the initial gate layers in the first region into a plurality of initial gate pillars, and the second trench partitions the initial gate layers in the second region into a first connection layer and a second connection layer; and

separating the plurality of initial gate pillars into the first gate array and the second gate array along the first direction.

14. The manufacturing method according to claim 13 , wherein the separating the plurality of initial gate pillars into the first gate array and the second gate array along the first direction comprises:

forming a second sacrificial layer in the first trench and the second trench;

forming a first support layer, a second support layer, and a third support layer that are spaced part along the first direction in the second sacrificial layer and the first laminated structure, wherein the first support layer connects the initial gate pillar and the first connection layer, the third support layer connects the initial gate pillar and the second connection layer, and the second support layer connects the initial gate pillars; and

removing a part of the second sacrificial layer, a part of the first sacrificial layer, and a part of the initial gate pillar at lateral sides of the second support layer of the first region, to form the first gate array and the second gate array; and

removing the remaining second sacrificial layer and first sacrificial layer.

15. The manufacturing method according to claim 14 , wherein the forming a dielectric layer on the first gate and the second gate, and forming a channel on the dielectric layer comprises:

forming dielectric layers on the first gate, the second gate, the first connection layer, and the second connection layer respectively.

16. The manufacturing method according to claim 15 , wherein the forming a first metal layer and a second metal layer comprises:

forming a second isolation layer between the first support layer and the second support layer, and forming a third isolation layer between the second support layer and the third support layer;

forming a third sacrificial layer between the second isolation layer and the second support layer, and between the second support layer and the third isolation layer; and

forming the first metal layer on the channel of the first gate, and forming the second metal layer on the channel of the second gate.

17. The manufacturing method according to claim 16 , wherein the forming a third metal layer and a fourth metal layer comprises:

forming a fourth sacrificial layer between the first support layer and the second isolation layer, and between the third isolation layer and the third support layer, wherein the fourth sacrificial layer covers the first connection layer and the second connection layer; and

forming the third metal layer on the channel of the first gate, and forming the fourth metal layer on the channel of the second gate.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (71)