IP Library › Granted Patent US 12,310,125
Granted Patent B2
US 12,310,125 · App. 17/432,913 · Granted May 20, 2025

Avalanche photodetector (variants) and method for manufacturing the same (variants)

Inventors: Nikolai Afanasevich Kolobov (Moscow, RU); Konstantin Yurevich Sitarskiy (Moscow, RU); Vitalii Emmanuilovich Shubin (Moscow, RU); Dmitrii Alekseevich Shushakov (Moscow, RU); Sergei Vitalevich Bogdanov (Moscow, RU)
Assignee: Dephan LLC
H10F30/225H10F71/1221H10F71/1385
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Quick Facts
Patent No.
US 12,310,125
App. No.
17/432,913
Granted
May 20, 2025
Kind
B2
Abstract

Method for manufacturing avalanche photodetector, including forming multiplication layer on wafer; etching closed groove on surface of the multiplication layer, so that depth of the closed groove is greater than or equal to thickness of the multiplication layer, but less than total thickness of the wafer and multiplication layer combined; filling the groove with highly-doped polycrystalline silicon of same conductivity type as multiplication layer; forming, on upper surface of multiplication layer, inside groove, avalanche amplifier as mesa structure, by forming contact layer on multiplication layer, while simultaneously forming photoconverter outside contact layer, and etching away portion of multiplication layer in the photoconverter to depth less than thickness of the multiplication layer; forming dielectric layer on multiplication layer where etching took place, its thickness equal to the depth of multiplication layer that was etched away; forming first electrode of transparent material on surfaces of contact and dielectric layers; forming second electrode.

Claims (26)

1. A method for manufacturing an avalanche photodetector, the method comprising:

forming a multiplication layer on an upper surface of a semiconductor wafer;

forming, on an upper surface of the multiplication layer at least one avalanche amplifier as a mesa structure, by (i) forming a contact layer on a portion of the upper surface of the multiplication layer, while simultaneously forming a photoconverter region as part of the multiplication layer outside the contact layer, and (ii) etching away a portion of the multiplication layer in the photoconverter region to a depth that is less than a thickness of the multiplication layer;

forming a dielectric layer on a surface of the multiplication layer where the etching took place, such that a thickness of the dielectric layer is equal to a depth of the multiplication layer in the photoconverter region that was previously etched away;

forming a first electrode of a transparent material on surfaces of both the contact layer and the dielectric layer;

forming a second electrode on a bottom surface of the semiconductor wafer.

2. The method of claim 1 , wherein the multiplication layer is formed using the epitaxy method.

3. The method of claim 1 , wherein the contact layer is made by doping the multiplication layer with a dopant that forms a layer with an opposite conductivity.

4. The method of claim 1 , further comprising forming a closed groove on a surface of the multiplication layer, so that a depth of the closed groove is greater than or equal to a thickness of the multiplication layer, but less than a total thickness of the semiconductor wafer and the multiplication layer combined, and filling the closed groove with highly-doped polycrystalline silicon of the same conductivity type as the multiplication layer, wherein the closed groove has a width of 1.5 μm to 2.0 μm.

5. The method of claim 1 , wherein a high-resistance layer is formed on the contact layer of the avalanche amplifier before the first electrode is formed.

6. A method for manufacturing an avalanche photodetector, the method comprising:

forming a multiplication layer on an upper surface of a semiconductor wafer;

etching a closed groove on a surface of the multiplication layer, so that a depth of the closed groove is greater than or equal to a thickness of the multiplication layer, but less than a total thickness of the semiconductor wafer and the multiplication layer combined;

filling the closed groove with highly-doped polycrystalline silicon of the same conductivity type as the multiplication layer;

forming, on an upper surface of the multiplication layer inside the closed groove at least one avalanche amplifier as a mesa structure, by (i) forming a contact layer on a portion of the upper surface of the multiplication layer, while simultaneously forming a photoconverter region as part of the multiplication layer outside the contact layer, and (ii) etching away a portion of the multiplication layer in the photoconverter region to a depth that is less than a thickness of the multiplication layer;

forming a dielectric layer on a surface of the multiplication layer where the etching took place, a thickness of the dielectric layer being equal to the depth of the multiplication layer in the photoconverter region that was etched away previously;

forming a first electrode of a transparent material on surfaces of both the contact layer and the dielectric layer;

forming a second electrode on a bottom surface of the semiconductor wafer.

7. The method of claim 6 , wherein the semiconductor wafer is made of a low-resistance material.

8. The method of claim 6 , wherein both the semiconductor wafer and the multiplication layer are made of the same semiconductor material.

9. The method of claim 6 , wherein the multiplication layer is formed using the epitaxy method.

10. The method of claim 6 , wherein the contact layer is made by doping the multiplication layer with a dopant that forms a layer with an opposite conductivity.

11. The method of claim 6 , wherein the closed groove has a width of 1.5 μm to 2.0 μm.

12. The method of claim 6 , wherein the closed groove is circular in plan view.

13. The method of claim 6 , wherein the closed groove is hexagonal in plan view.

14. The method of claim 6 , wherein the high-resistance layer is formed on the contact layer of the avalanche amplifier before the first electrode is formed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2021
From: SHUBIN, VITALII EMMANUILOVICH; SHUSHAKOV, DMITRII ALEKSEEVICH; KOLOBOV, NIKOLAI AFANASEVICH; SITARSKIY, KONSTANTIN YUREVICH; BOGDANOV, SERGEI VITALEVICH
To: DEPHAN LLC
Reel/Frame 057247/0720 →
Priority Claims (1)
RU RU2019106925 · Mar 12, 2019 · national
Continuity (1)
Related Publication 20220190183A1 · Jun 16, 2022
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