IP Library › Granted Patent US 12,310,249
Granted Patent B2
US 12,310,249 · App. 18/238,520 · Granted May 20, 2025

Semiconductor device and method for fabricating the same

Inventors: Hui-Lin Wang (Taipei, TW); Po-Kai Hsu (Tainan, TW); Hung-Yueh Chen (Hsinchu, TW); Yu-Ping Wang (Hsinchu, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10N50/01H10N50/80H10N50/85H10B61/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,310,249
App. No.
18/238,520
Granted
May 20, 2025
Kind
B2
Abstract

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.

Claims (14)

1. A semiconductor device, comprising:

a magnetic tunneling junction (MTJ) on a substrate;

a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, wherein the cap layer adjacent to two sides of the MTJ are asymmetrical;

a first inter-metal dielectric (IMD) layer around the MTJ and the cap layer, wherein a top surface of the cap layer is higher than a top surface of the first IMD layer; and

a stop layer between the cap layer and the first IMD layer.

2. The semiconductor device of claim 1 , further comprising:

a top electrode on the MTJ;

a metal interconnection under the MTJ; and

a second IMD layer around the metal interconnection, wherein the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer.

3. The semiconductor device of claim 2 , further comprising:

the stop layer on the first IMD layer and the top electrode; and

a third IMD layer on the stop layer.

4. The semiconductor device of claim 3 , wherein a sidewall of the stop layer is aligned with a sidewall of the top electrode.

5. The semiconductor device of claim 3 , wherein the cap layer is between the stop layer and the third IMD layer.

Priority Claims (1)
TW 108144115 · Dec 3, 2019 · national
Continuity (3)
Continuation 17738001 · May 5, 2022
Continuation 16732359 · Jan 2, 2020
Related Publication 20230403941A1 · Dec 14, 2023
References Cited (14)
US 6664190B2 · Chen et al. · 2003 [cited by applicant]
US 9018720B2 · Park · 2015 [cited by examiner]
US 9484530B2 · Toh · 2016 [cited by applicant]
US 10580968B1 · Yi · 2020 [cited by applicant]
US 20160020249A1 · Ko · 2016 [cited by examiner]
US 20170025471A1 · Bhushan · 2017 [cited by applicant]
US 20180040817A1 · Chuang · 2018 [cited by applicant]
US 20190036014A1 · Ha · 2019 [cited by applicant]
US 20200006638A1 · Chen · 2020 [cited by applicant]
US 20200135805A1 · Hsu · 2020 [cited by applicant]
US 20200136027A1 · Wu · 2020 [cited by applicant]
US 20200365795A1 · Chuang · 2020 [cited by applicant]
TW 201806114A · 2018 [cited by applicant]
TW 201926438A · 2019 [cited by applicant]