IP Library › Granted Patent US 12,313,878
Granted Patent B2
US 12,313,878 · App. 18/009,084 · Granted May 27, 2025

Optoelectronic device and method of manufacture thereof

Inventors: Aaron John Zilkie (Pasadena, CA); Henri Nykänen (Espoo, FI); Frank Peters (Dublin, IE); Charles Su-Chang Tsai (Pasadena, CA); Guomin Yu (Pasadena, CA)
Assignee: Rockley Photonics Limited
G02B6/12004G02B6/122G02B6/136G02B2006/12061G02B2006/12107G02B2006/12161
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Quick Facts
Patent No.
US 12,313,878
App. No.
18/009,084
Filed
Dec 8, 2022
Granted
May 27, 2025
Kind
B2
Art Unit
2874
USPC
385/14
Abstract

An optoelectronic device. The device comprises: a silicon-on-insulator platform, including a silicon waveguide, formed in a silicon device layer, a silicon substrate, and a cavity; a III-V semiconductor based device, located within the cavity of the silicon-on-insulator platform and containing a III-V semiconductor based waveguide which is coupled to the silicon waveguide. A region of a bed of the cavity, located between the III-V semiconductor based device and the substrate, includes a patterned surface, which is configured to interact with an optical signal within the III-V semiconductor based waveguide of the III-V semiconductor based device.

Claims (42)

1. An optoelectronic device, comprising:

a silicon-on-insulator platform, including a silicon waveguide formed in a silicon device layer, a silicon substrate, and a cavity; and

a III-V semiconductor based device, located within the cavity of the silicon-on-insulator platform and containing a III-V semiconductor based waveguide which is optically coupled to the silicon waveguide,

wherein a region of a bed of the cavity, located between the III-V semiconductor based device and the silicon substrate, includes a patterned surface, which is configured to interact with an optical signal within the III-V semiconductor based waveguide of the III-V semiconductor based device, and

wherein:

the patterned surface is a Bragg grating;

the patterned surface is a grating, and the grating and the III-V semiconductor based device form a distributed feedback or distributed Bragg reflector laser;

the patterned surface is a reflective pattern, so as to confine an optical mode of the III-V semiconductor based waveguide to the III-V semiconductor based waveguide; or

the patterned surface is a wave-guiding pattern.

2. The optoelectronic device of claim 1 , wherein the patterned surface is formed within one of: the silicon device layer, which forms the bed of the cavity; the silicon substrate, which forms the bed of the cavity; or a liner, which lines the bed of the cavity.

3. The optoelectronic device of claim 2 , wherein the patterned surface is formed within the liner, and wherein;

the liner is high index silicon nitride; or

the liner comprises three dielectric thin film layers in which a first bottom layer is silicon nitride, a middle second layer is silicon oxide, and a third top layer is high index silicon nitride in which the patterned surface is formed.

4. The optoelectronic device of claim 3 , wherein the total thickness of the first bottom layer of silicon nitride and the middle second layer of silicon oxide is equal to or substantially equal to the thickness of a BOX layer of the silicon-on-insulator platform.

5. The optoelectronic device of claim 3 , wherein the high index silicon nitride has a refractive index of 3.2+/−0.1 and thickness of 250 nm+/−100 nm.

6. An optoelectronic device, comprising:

a silicon-on-insulator platform, including a silicon waveguide formed in a silicon device layer, a silicon substrate, and a cavity; and

a III-V semiconductor based device, located within the cavity of the silicon-on-insulator platform and containing a III-V semiconductor based waveguide which is optically coupled to the silicon waveguide,

wherein a region of a bed of the cavity, located between the III-V semiconductor based device and the silicon substrate, includes a patterned surface, which is configured to interact with an optical signal within the III-V semiconductor based waveguide of the III-V semiconductor based device, and

wherein the region of the bed of the cavity includes an intermediate structure, and wherein the patterned surface is provided on the intermediate structure.

7. The optoelectronic device of claim 6 , wherein the intermediate structure projects from the region of the bed of the cavity, with the patterned surface contained in a surface distal from the bed of the cavity.

8. The optoelectronic device of claim 6 wherein the intermediate structure is a silicon-on-insulator chip which is bonded to the bed of the cavity.

9. The optoelectronic device of claim 1 , wherein the patterned surface is the Bragg grating.

10. An optoelectronic device, comprising:

a silicon-on-insulator platform, including a silicon waveguide formed in a silicon device layer, a silicon substrate, and a cavity; and

a III-V semiconductor based device, located within the cavity of the silicon-on-insulator platform and containing a III-V semiconductor based waveguide which is optically coupled to the silicon waveguide,

wherein a region of a bed of the cavity, located between the III-V semiconductor based device and the silicon substrate, includes a patterned surface, which is configured to interact with an optical signal within the III-V semiconductor based waveguide of the III-V semiconductor based device, and

wherein the bed of the cavity is formed of a dielectric, and the patterned surface is formed within the dielectric.

11. The optoelectronic device of claim 10 , wherein the dielectric is benzocyclobutene.

12. The optoelectronic device of claim 1 , further comprising one or more heaters, located within or on the bed of the cavity, and configured to tune an operating wavelength of the optoelectronic device.

13. The optoelectronic device of claim 12 , wherein:

a heater of the one or more heaters is a doped region of the bed of the cavity; or

the heater is a metal strip disposed on the bed of the cavity.

14. The optoelectronic device of claim 1 , wherein the patterned surface is the grating, and the grating and the III-V semiconductor based device form the distributed feedback or distributed Bragg reflector laser.

15. The optoelectronic device of claim 14 , wherein:

the grating is a partial grating which extends only part way along the III-V semiconductor based device; or

the patterned surface comprises a first grating and a second grating region, spaced in a guiding direction of the III-V semiconductor based waveguide by a non-grating region.

16. The optoelectronic device of claim 1 , wherein the patterned surface is the reflective pattern, so as to confine the optical mode of the III-V semiconductor based waveguide to the III-V semiconductor based waveguide.

17. The optoelectronic device of claim 1 , wherein the patterned surface is the wave-guiding pattern.

18. The optoelectronic device of claim 17 , wherein the III-V semiconductor based waveguide is wider at one end than a width in a central region of the III-V semiconductor based waveguide, such that an optical signal carried by the III-V semiconductor based waveguide towards the end of said waveguide is guided by the wave-guiding pattern.

19. A method of preparing the optoelectronic device of claim 1 , wherein the method comprises the step of:

etching the patterned surface into the region of the bed of the cavity.

Assignments (1)
SECURITY INTEREST Recorded Mar 19, 2023
From: ROCKLEY PHOTONICS LIMITED
To: WILMINGTON SAVINGS FUND SOCIETY, FSB, AS COLLATERAL AGENT
Reel/Frame 063287/0879 →
Priority Claims (4)
GB 2008698 · Jun 9, 2020 · national
GB 2008722 · Jun 9, 2020 · national
GB 2008731 · Jun 9, 2020 · national
GB 2101257 · Jan 29, 2021 · national
Continuity (2)
Provisional Application 63094857 · Oct 21, 2020
Related Publication 20230251419A1 · Aug 10, 2023
References Cited (39)
US 6888989B1 · Zhou et al. · 2005 [cited by applicant]
US 10197730B1 · Ngu et al. · 2019 [cited by applicant]
US 10509244B1 · Shank et al. · 2019 [cited by applicant]
US 20040245936A1 · Flower · 2004 [cited by applicant]
US 20100086255A1 · Ishizaka · 2010 [cited by applicant]
US 20110150024A1 · Dupont et al. · 2011 [cited by applicant]
US 20140321488A1 · Chen et al. · 2014 [cited by applicant]
US 20160211645A1 · Padullaparthi · 2016 [cited by applicant]
US 20160274319A1 · Krasulick · 2016 [cited by examiner]
US 20180057079A1 · Ono · 2018 [cited by applicant]
US 20180241176A1 · Abel et al. · 2018 [cited by applicant]
US 20180331500A1 · Cheung et al. · 2018 [cited by applicant]
US 20190140425A1 · Hahn et al. · 2019 [cited by applicant]
US 20190341744A1 · Chae · 2019 [cited by applicant]
US 20200041721A1 · Yu et al. · 2020 [cited by applicant]
US 20200076155A1 · Wu et al. · 2020 [cited by applicant]
CN 109560462A · 2019 [cited by applicant]
GB 2571269A · 2019 [cited by applicant]
GB 2586889A · 2021 [cited by applicant]
GB 2589092A · 2021 [cited by applicant]
GB 2589335A · 2021 [cited by applicant]
WO WO2017200620A2 · 2017 [cited by applicant]
Duggan, S., “Regrowth-free Monolithic Vertical Integration of Passive and Active Waveguides”, Integrated Photonics, PhD Thesis, University College Cork, Ireland, May 2, 2019, 171 pages. [cited by applicant]
International Search Report and Written Opinion of the International Searching Authority, mailed Sep. 13, 2021, corresponding to PCT/EP2021/065463, 17 pages. [cited by applicant]
Loi, R. et al., “Edge-Coupling of O-Band InP Etched-Facet Lasers to Polymer Waveguides on SOI by Micro-Transfer-Printing”, IEEE Journal of Quantum Electronics, Dec. 9, 2019, 8 pages, vol. 56, No. 1, IEEE. [cited by applicant]
U.K. Intellectual Property Office Combined Search and Examination Report, dated Nov. 30, 2020, for Patent Application No. GB2008698.9, 7 pages. [cited by applicant]
U.K. Intellectual Property Office Combined Search and Examination Report, dated Nov. 26, 2020, for Patent Application No. GB2008722.7, 6 pages. [cited by applicant]
U.K. Intellectual Property Office Combined Search and Examination Report, dated Nov. 27, 2020, for Patent Application No. GB2008731.8, 6 pages. [cited by applicant]
U.K. Intellectual Property Office Combined Search and Examination Report, dated Jul. 16, 2021, for Patent Application No. GB2101257.0, 5 pages. [cited by applicant]
U.K. Intellectual Property Office Combined Search and Examination Report, dated Nov. 3, 2021, for Patent Application No. GB2108233.4, 8 pages. [cited by applicant]
U.K. Intellectual Property Office Examination Report, dated Aug. 30, 2022, for Patent Application No. GB2108233.4, 2 pages. [cited by applicant]
U.K. Intellectual Property Office Examination Report, dated Sep. 28, 2022, for Patent Application No. GB2008731.8, 3 pages. [cited by applicant]
U.K. Intellectual Property Office Search Report, dated Feb. 28, 2023, for Patent Application No. GB2008731.8, 3 pages. [cited by applicant]
U.K. Intellectual Property Office Search Report, dated Sep. 28, 2022, for Patent Application No. GB2008731.8, 3 pages. [cited by applicant]
Zhang, J. et al., “Micro-transfer-printed III-V-on-silicon C-band Distributed Bragg Reflector Laser”, 2019, IEEE 16th International Conference on Group IV Photonics, Aug. 28, 2019, 2 pages, IEEE. [cited by applicant]
Zhang, J. et al., “Transfer-printing-based integration of a III-V-on-silicon distributed feedback laser”, Optics Express, Mar. 27, 2018, pp. 8821-8830, vol. 26, No. 7, Optical Society of America. [cited by applicant]
International Preliminary Report on Patentability, International Application No. PCT/EP2021/065463, PCT/IB/373, dated Dec. 13, 2022, 9 pages. [cited by applicant]
Juvert Joan et al: “Integration of III-V light sources on a silicon photonics circuit by transfer printing”, 2017 IEEE 14th International Conference On Group IV Photonics (GFP), IEEE, Aug. 23, 2017 (Aug. 23, 2017), pp. … [cited by applicant]
International Search Report and Written Opinion, International Application No. PCT/EP2021/065463, PCT/ISA/210, 12 pages. [cited by applicant]