Memory controller operable in data loop-back mode
A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.
1. A memory control component to control a dynamic random access memory (DRAM) device, the memory control component comprising:
a data interface to:
transmit write data to be stored within a core of the DRAM device while in a data transfer mode; and
transmit a calibration pattern to the DRAM device while in a data loopback mode;
a timing interface to transmit a differential timing signal to the DRAM device, the DRAM device to generate calibration-pattern feedback at least in part by sampling the calibration pattern using the differential timing signal while in the data loopback mode; and
a signaling contact, distinct from the data interface, to receive the calibration-pattern feedback from the DRAM device while in the data loopback mode.
2. The memory control component of claim 1 wherein the signaling contact to receive the calibration-pattern feedback comprises a contact to receive, as at least part of the calibration-pattern feedback, digital samples of the calibration pattern generated within the DRAM device by sampling the calibration pattern using the differential timing signal.
3. The memory control component of claim 2 wherein the contact to receive the digital samples of the calibration pattern generated within the DRAM device comprises a contact to receive a plurality of pairs of values, each of the pairs of values generated within the DRAM device by sampling the calibration pattern twice per cycle of the differential timing signal.
4. The memory control component of claim 1 wherein the data interface comprises circuitry to receive read data retrieved from the core of the DRAM device while in the data transfer mode.
5. The memory control component of claim 1 further comprising a command interface to transmit to the DRAM device one or more commands that render the DRAM device into the data loopback mode.
6. The memory control component of claim 5 wherein the command interface to transmit the one or more commands that render the DRAM device into the data loopback mode comprises circuitry configure the DRAM device to (i) route a plurality of digital samples of the calibration pattern, generated within the DRAM device by sampling the calibration pattern using the differential timing signal, to a transmitter circuit of the DRAM device and (ii) enable the transmitter circuit of the DRAM device to transmit the plurality of digital samples onto a data signal line that is to be coupled to the signaling contact.
7. The memory control component of claim 1 wherein the timing interface to transmit the differential timing signal to the DRAM device comprises circuitry to transmit the differential timing signal synchronously with respect to transmission of the calibration pattern via the data interface.
8. The memory control component of claim 1 wherein the signaling contact to receive the calibration-pattern feedback comprises a contact to receive, as at least part of the calibration-pattern feedback, a plurality of digital values generated within a data receiver circuit of the DRAM device and conveyed to a data transmitter circuit of the DRAM device via a data loopback path of the DRAM device, the plurality of digital values being generated within the data receiver circuit of the DRAM device by sampling the calibration pattern using the differential timing signal while in the data loopback mode.
9. The memory control component of claim 8 further comprising a command interface to transmit to the DRAM device one or more commands that direct the DRAM device to switchably form the data loopback path.
10. The memory control component of claim 8 wherein the command interface to transmit to the DRAM device the one or more commands that direct the DRAM device to switchably form the data loopback path comprises circuitry to transmit a calibration command that directs the DRAM device to couple an output of the data receiver circuit to an input of the data transmitter circuit via a multiplexer circuit.
11. A method of operation within a memory control component having a timing interface, a data interface, and a signaling contact distinct from the data interface, the method comprising:
transmitting a differential timing signal to a dynamic random memory access (DRAM) device via the timing interface;
transmitting to the DRAM device via the data interface (i) write data to be stored within a core of the DRAM device while in a data transfer mode and (ii) a calibration pattern to be sampled by the DRAM device using the differential timing signal while in a data loopback mode; and
receiving, via the signaling contact, calibration-pattern feedback generated within the DRAM device at least in part by sampling the calibration pattern using the differential timing signal while in the data loopback mode.
12. The method of claim 11 wherein receiving the calibration-pattern feedback comprises receiving, as at least part of the calibration-pattern feedback, digital samples of the calibration pattern generated within the DRAM device by sampling the calibration pattern using the differential timing signal.
13. The method of claim 12 wherein receiving the digital samples of the calibration pattern generated within the DRAM device comprises receiving a plurality of pairs of values, each of the pairs of values generated within the DRAM device by sampling the calibration pattern twice per cycle of the differential timing signal.
14. The method of claim 11 further comprising receiving, from the DRAM device via the data interface, read data retrieved from the core of the DRAM device while in the data transfer mode.
15. The method of claim 11 further comprising transmitting one or more commands to the DRAM device to render the DRAM device into the data loopback mode.
16. The method of claim 15 wherein transmitting the one or more commands to render the DRAM device into the data loopback mode comprises transmitting one or more commands to configure the DRAM device to (i) route a plurality of digital samples of the calibration pattern, generated within the DRAM device by sampling the calibration pattern using the differential timing signal, to a transmitter circuit of the DRAM device and (ii) enable the transmitter circuit of the DRAM device to transmit the plurality of digital samples onto a data signal line coupled to the signaling contact.
17. The method of claim 11 wherein transmitting the differential timing signal to the DRAM device comprises transmitting the differential timing signal synchronously with respect to transmission of the calibration pattern via the data interface.
18. The method of claim 11 wherein receiving the calibration-pattern feedback comprises receiving, as at least part of the calibration-pattern feedback, a plurality of digital values generated within a data receiver circuit of the DRAM device and conveyed to a data transmitter circuit of the DRAM device via a data loopback path of the DRAM device, the plurality of digital values being generated within the data receiver circuit of the DRAM device by sampling the calibration pattern using the differential timing signal while in the data loopback mode.
19. The method of claim 18 further comprising transmitting to the DRAM device one or more commands that direct the DRAM device to switchably form the data loopback path.
20. The method of claim 18 wherein transmitting to the DRAM device the one or more commands that direct the DRAM device to switchably form the data loopback path comprises transmitting a calibration command that directs the DRAM device to couple an output of the data receiver circuit to an input of the data transmitter circuit via a multiplexer circuit.
21. A memory control component comprising:
a data interface including means for transmitting write data to be stored within a core of a dynamic random access memory (DRAM) device while in a data transfer mode and means for transmitting a calibration pattern to the DRAM device while in a data loopback mode;
means for transmitting a differential timing signal to the DRAM device, the DRAM device to generate calibration-pattern feedback at least in part by sampling the calibration pattern using the differential timing signal while in the data loopback mode; and
means, distinct from the data interface, for receiving the calibration-pattern feedback from the DRAM device while in the data loopback mode.