In-memory database (IMDB) acceleration through near data processing
An accelerator is disclosed. The accelerator may include an on-chip memory to store a data from a database. The on-chip memory may include a first memory bank and a second memory bank. The first memory bank may store the data, which may include a first value and a second value. A computational engine may execute, in parallel, a command on the first value in the data and the command on the second value in the data in the on-chip memory. The on-chip memory may be configured to load a second data from the database into the second memory bank in parallel with the computation engine executing the command on the first value in the data and executing the command on the second value in the data.
1. An accelerator, comprising:
a memory including a first memory address and a second memory address; and
a processor to execute a command on a first value and a second value in the first memory address in the memory,
wherein the memory is configured to load a third value into the second memory address, and
wherein the accelerator is configured to execute the command on the third value in the second memory address.
2. The accelerator according to claim 1 , wherein the first value and the second value are stored in the memory of the accelerator.
3. The accelerator according to claim 1 , wherein the memory is configured to load the first value and the second value from an output buffer of the accelerator.
4. The accelerator according to claim 3 , wherein:
the memory is configured to store an uncompressed first value and an uncompressed second value; and
the accelerator further comprises an input buffer storing a compressed first value and a compressed second value.
5. The accelerator according to claim 4 , further comprising a decompressor to generate the uncompressed first value from the compressed first value.
6. The accelerator according to claim 1 , wherein the first memory address includes a first memory unit and a second memory unit, the first memory unit storing the first value and the second memory unit storing the second value.
7. The accelerator according to claim 1 , further comprising an output memory to store a result of the command.
8. The accelerator according to claim 7 , wherein the accelerator is configured to transfer the result of the command from the output memory to a page cache.
9. The accelerator according to claim 1 , wherein the accelerator is configured to return a result of the processor executing the command on the first value and the second value in the first memory address to an application.
10. A system, comprising:
a host processor;
a host memory coupled to the host processor; and
an accelerator, including:
a memory including a first memory address and a second memory address; and
a processor to execute a command on a first value and a second value in the first memory address in the memory,
wherein the memory is configured to load a third value into the second memory address, and
wherein the accelerator is configured to execute the command on the third value in the second memory address.
11. The system according to claim 10 , wherein the first value and the second value are stored in the memory of the accelerator.
12. A system according to claim 10 , wherein the first memory address includes a first memory unit and a second memory unit, the first memory unit storing the first value and the second memory unit storing the second value.
13. The system according to claim 10 , wherein the system is configured to return a result of the processor executing the command on the first value and the second value in the first memory address to an application.
14. A method, comprising:
loading a first value and a second value into a first memory address of a memory of an accelerator;
executing a command on the first value and the second value in the first memory address to produce a result; and
loading a third value into a second memory address of the memory,
wherein the accelerator is configured to execute the command on the third value in the second memory address.
15. The method according to claim 14 , wherein loading the first value and the second value into the first memory address of the memory of the accelerator includes copying the first value and the second value from a second memory of the accelerator into the memory of the accelerator.
16. The method according to claim 14 , wherein loading the first value and the second value into the first memory address of the memory of the accelerator includes copying the first value and the second value from an output buffer of the accelerator into the memory of the accelerator.
17. The method according to claim 14 , wherein loading the first value and the second value into the first memory address of the memory of the accelerator includes:
loading a compressed first value into the accelerator; and
decompressing the compressed first value to generate the first value.
18. The method according to claim 17 , wherein loading the compressed first value includes loading the compressed first value into an input buffer of the accelerator.
19. The method according to claim 17 , wherein decompressing the compressed first value to generate the first value includes storing the first value in an output buffer of the accelerator.
20. The method according to claim 14 , further comprising storing the result in an output memory.
21. The method according to claim 20 , further comprising copying the result from the output memory into a page cache.
22. The method according to claim 14 , wherein:
loading the first value and the second value into the first memory address of the memory of the accelerator includes:
loading the first value into a first memory unit of the first memory address of the accelerator; and
loading the second value into a second memory unit of the first memory address of the accelerator; and
executing the command on the first value and the second value in the first memory address to produce the result includes:
executing the command on the first value in the first memory unit;
executing the command on the second value in the second memory unit; and
producing the result based at least in part on executing the command on the first value in the first memory unit and executing the command on the second value in the second memory unit.