Read disturb management for memory
Methods, systems, and devices for read disturb management for memory are described. In some instances, data may be read from a first page of a virtual block of a memory system. If the data includes one or more errors, the memory system may read data from a second page of the virtual block and determine whether one or more errors exist in the data. The memory system may continue reading pages of the virtual block until a page includes no (or relatively few errors). The memory system may then refresh the pages.
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
read data from a first page of a virtual block of the one or more memory devices, wherein the virtual block comprises a plurality of pages that comprises the first page and a second page;
determine whether data stored to the second page of the virtual block comprises one or more errors based at least in part on determining that the data read from the first page of the virtual block comprises one or more errors, wherein the one or more errors of the second page are associated with a shift in a threshold voltage of one or more memory cells of the second page, wherein the shift in the threshold voltage is based at least in part on reading the data from the first page;
determine that data stored to the plurality of pages of the virtual block comprise one or more errors based at least in part on determining that the data stored to the second page of the virtual block comprises one or more errors, wherein the plurality of pages comprise the second page;
postpone refreshing the plurality of pages of the virtual block based at least in part on a quantity of the plurality of pages satisfying a threshold quantity of pages; and
refresh the second page of the virtual block based at least in part on postponing refreshing the plurality of pages of the virtual block.
2. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
refresh the first page of the virtual block based at least in part on determining that the data stored to the first page of the virtual block comprises one or more errors.
3. The memory system of claim 2 , wherein the processing circuitry is further configured to cause the memory system to:
determine that the one or more errors associated with the data stored to the first page of the virtual block satisfies a first threshold, wherein refreshing the first page of the virtual block is based at least in part on determining that one or more errors associated with the first page of the virtual block satisfies the first threshold.
4. The memory system of claim 3 , wherein the first threshold is associated with a bit error rate, a quantity of errors, or both.
5. The memory system of claim 2 , wherein the processing circuitry is further configured to cause the memory system to:
determine that a quantity of access operations performed on the first page of the virtual block satisfies a second threshold, wherein refreshing the first page of the virtual block is based at least in part on determining that the quantity of access operations performed on the first page of the virtual block satisfies the second threshold.
6. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
refresh, after postponing refreshing the plurality of pages of the virtual block, the plurality of pages of the virtual block.
7. The memory system of claim 1 , wherein determining whether data stored to the second page of the virtual block comprises one or more errors comprises the processing circuitry configured to cause the memory system to:
read a value stored to a component of the one or more memory devices, wherein the value indicates whether the data stored to the second page of the virtual block comprises one or more errors.
8. The memory system of claim 1 , wherein refreshing the second page of the virtual block comprises the processing circuitry configured to cause the memory system to:
read the data from the second page of the virtual block based at least in part on determining that the data read from the second page of the virtual block comprises one or more errors; and
write the data associated with the second page of the virtual block to a third page of a second virtual block.
9. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
refrain from refreshing a third page of the virtual block based at least in part on determining that data stored to the third page of the virtual block does not comprise one or more errors.
10. The memory system of claim 9 , wherein:
the first page is adjacent to the second page.
11. The memory system of claim 10 , wherein the processing circuitry is further configured to cause the memory system to:
refrain from refreshing a fourth page of the virtual block based at least in part on determining that data stored to the fourth page does not comprise one or more errors, wherein the fourth page is adjacent to the first page, and wherein refraining from refreshing the fourth page is based at least in part on determining that the fourth page does not comprise one or more errors after correcting one or more errors of the first page and the second page.
12. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
determine that data stored to a third page of the virtual block comprises one or more errors based at least in part on determining that the data read from the second page of the virtual block comprises one or more errors; and
refresh the third page of the virtual block based at least in part on determining that the data stored to the third page of the virtual block comprises one or more errors.
13. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
determine that data stored to a fourth page of the virtual block comprises a bit error rate that satisfies a third threshold; and
refresh the fourth page of the virtual block based at least in part on determining that the bit error rate satisfies the third threshold.
14. The memory system of claim 13 , wherein the processing circuitry is further configured to cause the memory system to:
determine that data stored to a fifth page of the virtual block comprises a bit error rate that does not satisfy the third threshold, wherein the fifth page is adjacent to the fourth page; and
refrain from refreshing the fifth page of the virtual block based at least in part on determining that the bit error rate of the fifth page of the virtual block does not satisfy the third threshold.
15. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
read the data from the second page of the virtual block based at least in part on determining that the data read from the first page of the virtual block comprises one or more errors, wherein determining whether the data stored to the second page of the virtual block comprises one or more errors is based at least in part on reading the data from the second page of the virtual block.
16. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
determine that the data read from the first page of the virtual block comprises one or more errors based at least in part on reading the data from the first page, wherein determining whether the data stored to the second page of the virtual block comprises one or more errors is based at least in part on determining that the data read from the first page of the virtual block comprises one or more errors.
17. A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:
read data from a first page of a virtual block of one or more memory devices, wherein the virtual block comprises a plurality of pages that comprises the first page and a second page;
determine whether data stored to the second page of a virtual block comprises one or more errors based at least in part on determining that the data read from the first page of the virtual block comprises one or more errors, wherein the one or more errors of the second page are associated with a shift in a threshold voltage of one or more memory cells of the second page, wherein the shift in the threshold voltage is based at least in part on reading the data from the first page;
determine that data stored to the plurality of pages of the virtual block comprise one or more errors based at least in part on determining that the data stored to the second page of the virtual block comprises one or more errors, wherein the plurality of pages comprise the second page;
postpone refreshing the plurality of pages of the virtual block based at least in part on a quantity of the plurality of pages satisfying a threshold quantity of pages; and
refresh the second page of the virtual block based at least in part on postponing refreshing the plurality of pages of the virtual block.
18. The non-transitory computer-readable medium of claim 17 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:
refresh the first page of the virtual block based at least in part on determining that the data stored to the first page of the virtual block comprises one or more errors.
19. The non-transitory computer-readable medium of claim 18 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:
determine that the one or more errors associated with the data stored to the first page of the virtual block satisfies a first threshold, wherein refreshing the first page of the virtual block is based at least in part on determining that one or more errors associated with the first page of the virtual block satisfies the first threshold.
20. The non-transitory computer-readable medium of claim 17 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:
refrain from refreshing a third page of the virtual block based at least in part on determining that data stored to the third page of the virtual block does not comprise one or more errors.
21. A method by a memory system, comprising:
reading data from a first page of a virtual block of one or more memory devices, wherein the virtual block comprises a plurality of pages that comprises the first page and a second page;
determining whether data stored to the second page of the virtual block comprises one or more errors based at least in part on determining that the data read from the first page of the virtual block comprises one or more errors, wherein the one or more errors of the second page are associated with a shift in a threshold voltage of one or more memory cells of the second page, wherein the shift in the threshold voltage is based at least in part on reading the data from the first page;
determining that data stored to the plurality of pages of the virtual block comprise one or more errors based at least in part on determining that the data stored to the second page of the virtual block comprises one or more errors, wherein the plurality of pages comprise the second page;
postponing refreshing the plurality of pages of the virtual block based at least in part on a quantity of the plurality of pages satisfying a threshold quantity of pages; and
refreshing the second page of the virtual block based at least in part on postponing refreshing the plurality of pages of the virtual block.
22. The method of claim 21 , further comprising:
refraining from refreshing a third page of the virtual block based at least in part on determining that data stored to the third page of the virtual block does not comprise one or more errors.