Granted Patent B2

US 12,314,644 · App. 18/356,426 · Granted May 27, 2025

Inventors: Ankita Patidar (Hsinchu, TW); Sandeep Kumar Goel (Hsinchu, TW); Yun-Han Lee (Hsinchu, TW)

Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.; TSMC NANJING COMPANY, LIMITED

G06F30/327G06F30/398G06F30/3308G06F30/333G06F2119/02G06F2119/18

Abstract

Claims (112)

1. A method, said method executed at least partially by a processor and comprising:

creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram, wherein each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths;

testing at least one path in a group among the plurality of groups; and

in response to said testing indicating that the at least one path fails, modifying at least one of

the IC layout diagram,

at least a portion of at least one library having cells included in the IC layout diagram, or

a manufacturing process for manufacturing an IC corresponding to the IC layout diagram,

wherein

the plurality of features comprises:

at least one numerical feature having a numerical value, and

at least one categorical feature having a non-numerical value,

the method further comprises converting the non-numerical value of the at least one categorical feature into a converted numerical value, and

said creating the plurality of groups is based on

the numerical value of the at least one numerical feature, and

the converted numerical value of the at least one categorical feature.

2. The method of claim 1 , wherein

said modifying changes not only the at least one path that fails said testing, but also other paths in the same group as the at least one path.

3. The method of claim 1 , further comprising:

generating at least one test pattern for the at least one path in said group,

wherein said testing comprises testing the at least one path using the generated at least one test pattern.

4. The method of claim 1 , wherein

the plurality of features comprises at least one of

one or more timing features in a timing report of a static timing analysis (STA) of the IC layout diagram,

one or more logical features in an IC schematic corresponding to the IC layout diagram, or

one or more physical features of elements in the IC layout diagram.

5. The method of claim 1 , further comprising:

removing at least one feature from the plurality of features to obtain a reduced set of features including the dominant features of the plurality of groups.

6. The method of claim 5 , wherein

in said removing, the at least one removed feature comprises a feature which has no variation across the plurality of paths.

7. The method of claim 1 , wherein

the at least one numerical feature comprises numerical features having numerical values,

the at least one categorical feature comprises categorical features having non-numerical values, and

said converting comprises converting the non-numerical values of the categorical features into converted numerical values,

the method further comprising:

normalizing the numerical values of the numerical features and the converted numerical values of the categorical features; and

using the normalized values in said creating the plurality of groups.

8. The method of claim 7 , further comprising:

for each feature among the plurality of features, determining a correlation coefficient between

the normalized values of said feature in the plurality of paths, and

the normalized values of slack in the plurality of paths; and

removing, from the plurality of features, at least one feature with the correlation coefficient within a predetermined range, to obtain a reduced set of features including the dominant features of the plurality of groups.

9. The method of claim 7 , wherein

the categorical features comprise:

pin names or instance names which, in said converting, are converted into the corresponding converted numerical values based on hierarchy levels associated with the pin names or instance names,

cell features which, in said converting, are split into cell function types and process parameters, and then the cell function types and the process parameters are converted into the corresponding converted numerical values, and

other features which, in said converting, are converted into the corresponding converted numerical values using ordinal encoding.

10. The method of claim 1 , wherein

said creating the plurality of groups comprises:

clustering the plurality of paths into a plurality of clusters,

determining the dominant feature for each cluster among the plurality of clusters, and

among the plurality of clusters,

designating each cluster having the dominant feature different from dominant features of other clusters as a group among the plurality of groups, and

merging clusters having the same dominant feature to obtain a further group among the plurality of groups.

11. The method of claim 10 , wherein

said determining the dominant feature for each cluster among the plurality of clusters comprises

calculating CB nx =(CM nx −DS x )/DS x ,

where

CB nx is a biasing of feature x in cluster n,

CM nx is a mean value of feature x in the paths in cluster n, and

DS x is a mean value of feature x in the plurality of paths, and

in response to (CB nx /Σ i=1 m CB n i) being greater than a predetermined threshold, determining that feature x is the dominant feature of cluster n, where the plurality of features includes m features.

12. The method of claim 11 , wherein

said determining the dominant feature for each cluster among the plurality of clusters further comprises

in response to no cluster having (CB nx /Σ i=1 m CB n i) greater than the predetermined threshold, designating feature x as the dominant feature of the cluster with the greatest (CB nx /Σ i=1 m CB n i).

13. The method of claim 10 , wherein

said clustering comprises K-means clustering.

14. A system, comprising a processor configured to:

extract a plurality of features of a plurality of paths in an integrated circuit (IC) layout diagram,

encode the plurality of features,

based on the plurality of encoded features, create a plurality of groups of paths from the plurality of paths, wherein each group among the plurality of groups has a unique dominant feature among the plurality of features,

perform a test of at least one path in at least one group among the plurality of groups, and

in response to the test indicating that the at least one path fails, cause modification of at least one of

the IC layout diagram,

at least a portion of at least one library having cells included in the IC layout diagram, or

a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

15. The system of claim 14 , wherein

the processor is configured to extract the plurality of features as

one or more timing features from a timing report of a static timing analysis (STA) of the IC layout diagram,

one or more logical features from an IC schematic corresponding to the IC layout diagram, and

one or more physical features of elements in the IC layout diagram.

16. The system of claim 14 , wherein

the processor is configured to remove a feature which has no variation across the plurality of paths from the plurality of features.

17. The system of claim 14 , wherein

the plurality of features comprises:

numerical features having numerical values, and

categorical features having non-numerical values,

the processor is further configured to

convert non-numerical values of the categorical features into converted numerical values,

normalize the numerical values of the numerical features and the converted numerical values of the categorical features,

use the normalized values to determine correlation coefficients between slack and the plurality of features, and

remove features with the correlation coefficients within a predetermined range from the plurality of features.

18. A computer program product, comprising a non-transitory, computer-readable recording medium containing instructions therein which, when executed by a processor, cause the processor to

create a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram, wherein each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths, and the plurality of features comprises at least one of:

a logical feature in an IC schematic corresponding to the IC layout diagram, or

a physical feature of at least one element in the IC layout diagram,

perform a test of at least one path in a group among the plurality of groups; and

in response to the at least one path failing the test, and based on the unique dominant feature of the group containing the at least one path failing the test, cause modification of at least one of

the IC layout diagram,

at least a portion of at least one library having cells included in the IC layout diagram, or

a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.

19. The computer program product of claim 18 , wherein the instructions, when executed by the processor, further cause the processor to

cluster the plurality of paths into a plurality of clusters, and

determine the dominant feature for each cluster among the plurality of clusters by

calculating CB nx =(CM nx −DS x )/DS x ,

where

CB nx is a biasing of feature x in cluster n,

CM nx is a mean value of feature x in the paths in cluster n, and

DS x is a mean value of feature x in the plurality of paths, and

in response to (CB nx /Σ i=1 m CB n i) being greater than a predetermined threshold, determining that feature x is the dominant feature of cluster n, where the plurality of features includes m features, and

in response to no cluster having (CB nx /Σ i=1 m CB n i) greater than the predetermined threshold, designating feature x as the dominant feature of the cluster with the greatest (CB nx /Σ i=1 m CB n i).

20. The computer program product of claim 18 , wherein

the unique dominant feature of a group among the plurality of groups is the physical feature of the at least one element in the IC layout diagram.

Assignments (1)

Priority Claims (1)

Continuity (3)

References Cited (39)