Granted Patent B2

US 12,315,124 · App. 17/667,817 · Granted May 27, 2025

Inventors: Sebdani Mahmood Mazrouei (Markham, CA); Kumar Anandabairavasamy Anand (Richmond, CA); Hideki Matsuda (Chino, JP)

Assignee: SEIKO EPSON CORPORATION

G06T7/0002G06T7/11G06T11/60G06T2207/20021

Abstract

Claims (60)

1. A circuit device comprising:

a register configured to store a cyclic redundancy check (CRC) expected value of a known image data of a known image in advance, the CRC expected value being obtained by performing image processing on the known image data in advance;

an image processing circuit configured to:

receive target image data, the target image data being formed by adding:

effective image data corresponding to an effective image;

to the known image data corresponding to the known image; and

execute the image processing on the target image data so as to output:

processed effective image data subjected to the image processing, the processed effective image data corresponding to a processed effective image; and

processed known image data subjected to the image processing, the processed known image data corresponding to a processed known image, the processed known image data having the CRC expected;

a CRC calculation circuit configured to obtain a CRC value based on the processed known image data; and

a determination circuit configured to determine correctness of the image processing by comparing the CRC value of the processed known image data with the CRC expected value,

wherein the processed effective image is located in an effective image region that is displayed on a screen, and

the processed known image is located in a non-display region that is not displayed on the screen.

2. The circuit device according to claim 1 , wherein the non-display region is a region corresponding to a blanking period.

3. The circuit device according to claim 1 , wherein the effective image region is divided into first to mth effective image regions, wherein m is an integer of 2 or more, and

the non-display region includes an adjacent region between two effective image regions of the first to mth effective image regions.

4. The circuit device according to claim 1 , further comprising: a register configured to store the CRC expected value in advance.

5. The circuit device according to claim 1 , wherein

the CRC expected value is added to the non-display region together with the known image data.

6. The circuit device according to claim 1 , wherein the image processing circuit is further configured to:

execute the image processing on the target image data to generate processed target image data; and

extract the processed effective image data by removing the processed known image data from the processed target image data.

7. The circuit device according to claim 1 , further comprising:

another image processing circuit, wherein

the image processing circuit is configured to execute the image processing on the target image data to generate first processed target image data, and the first processed target image data includes the processed effective image data and the processed known image data, and

the another image processing circuit is configured to execute another image processing on the first processed target image data to output another processed effective image data and another processed known image data.

8. The circuit device according to claim 7 , further comprising:

another CRC calculation circuit configured to obtain another CRC value based on the another processed known image data; and

another determination circuit configured to determine correctness of the another image processing by comparing the another CRC value with another CRC expected value of the another processed known image data.

9. A circuit device comprising:

a register configured to store a cyclic redundancy check (CRC) expected value of a known image data of a known image in advance, the CRC expected value being obtained by performing image processing on the known image data in advance;

a receiving circuit configured to receive effective image data;

a known image adding circuit configured to add the known image data to the

effective image data to output processed target image data;

first to nth image processing circuits, wherein n is an integer of 2 or more;

first to nth CRC calculation circuits;

first to nth determination circuits;

a known image removing circuit; and

a transmission circuit, wherein

the first image processing circuit of the first to nth image processing circuits is configured to execute first image processing on the processed target image data to output first processed image data including first processed effective image data which is the effective image data subjected to the first image processing and first processed known image data which is the known image data subjected to the first image processing,

an ith image processing circuit, wherein i is an integer of 2 or more and n or less of the first to nth image processing circuits is configured to execute ith image processing on i-1th processed image data to output ith processed image data including ith processed effective image data which is i-1th processed effective image data subjected to the ith image processing and ith processed known image data which is i-1th processed known image data subjected to the ith image processing,

a kth CRC calculation circuit, wherein k is an integer of 1 or more and n or less of the first to nth CRC calculation circuits is configured to obtain a kth CRC value based on kth processed known image data,

a kth determination circuit of the first to nth determination circuits is configured to determine correctness of kth image processing by comparing a kth CRC expected value with the kth CRC value of the kth processed known image data,

the known image removing circuit is configured to extract nth processed effective image data by removing nth processed known image data from nth processed image data, the nth processed known image data corresponds to nth processed known image, and the nth processed effective image data corresponds to nth processed effective image,

the transmission circuit is configured to transmit the nth processed effective image data,

the nth processed effective image is located in an effective image region that is displayed on a screen, and

the nth processed known image is located in a non-display region that is not displayed on the screen.

10. An electronic apparatus comprising the circuit device according to claim 1 .

11. An image processing method, comprising:

storing a cyclic redundancy check (CRC) expected value of a known image data of a known image in advance, the CRC expected value being obtained by performing image processing on the known image data in advance;

receiving target image data, the target image data being formed by adding:

effective image data corresponding to an effective image;

to the known image data corresponding to the known image; and

executing the image processing on the target image data so as to output:

processed effective image data subjected to the image processing, the processed effective image data corresponding to a processed effective image; and

processed known image data subjected to the image processing, the processed known image data corresponding to a processed known image, the processed known image data having the CRC expected value;

obtaining a CRC value based on the processed known image data; and

determining correctness of the image processing by comparing the CRC value of the processed known image data with the CRC expected value,

wherein the processed effective image is located in an effective image region that is displayed on a screen, and

the processed known image is located in a non-display region that is not displayed on the screen.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (15)