Cryogenic memory cell and memory device

1. A cryogenic memory cell, comprising:

a spin moment transfer device comprising an input terminal and a ground terminal, wherein the input terminal of the spin moment transfer device is configured to receive an input write current, the spin moment transfer device converts the write current into a spin polarization current and changes its magnetic polarization direction under the action of the spin polarization current to achieve write storage of 0 and 1; and

a nano-superconducting quantum interference device comprising an input/output terminal and a ground terminal, wherein the input/output terminal of the nano-superconducting quantum interference device is configured to receive an input read current and output a readout signal, the ground terminal of the nano-superconducting quantum interference device is in common-ground connection with the ground terminal of the spin moment transfer device, the nano-superconducting quantum interference device undergoes a magnetic flux change under the action of a change in the magnetic polarization direction of the spin moment transfer device, thereby switching between a superconducting state and a non-superconducting state under a read current bias, to achieve read-out of 0 and 1.

2. The cryogenic memory cell according to claim 1 , wherein the spin moment transfer device comprises a fixed magnet-containing layer, a metal layer, and a free magnetic layer stacked together, the fixed magnet-containing layer is configured to convert the write current into a spin polarization current, and the free magnetic layer changes the magnetic polarization direction when the spin polarization current flows therethrough, to achieve write storage of 0 and 1.

3. The cryogenic memory cell according to claim 1 , wherein the spin moment transfer device has a feature size of less than or equal to 100 nm, and the spin moment transfer device has a resistance ranging from 1 ohm to 10 ohm, and the nano-superconducting quantum interference device has a feature size of less than or equal to 100 nm.

4. A cryogenic memory cell, comprising:

a spin moment transfer device comprising an input terminal and a ground terminal, wherein the input terminal of the spin moment transfer device serves as a first input terminal of the cryogenic memory cell to receive an input first write current;

a nano-superconducting quantum interference device comprising an input/output terminal and a ground terminal, the input/output terminal of the nano-superconducting quantum interference device serves as an input/output terminal of the cryogenic memory cell to receive an input first read current and output a readout signal; and

an inductor coil comprising an input terminal and a ground terminal, wherein the input terminal of the inductor coil serves as a second input terminal of the cryogenic memory cell to receive an input second write current and second read current, the ground terminal of the inductor coil is in common-ground connection with the ground terminal of the spin moment transfer device and the ground terminal of the nano-superconducting quantum interference device, and the ground terminal of the inductor coil, the ground terminal of the spin moment transfer device, and the ground terminal of the nano-superconducting quantum interference device together serve as a ground terminal of the cryogenic memory cell, wherein

in a write operation, under the action of the second write current, the inductor coil generates a pulsed magnetic field, which is coupled to the spin moment transfer device, and the spin moment transfer device undergoes a magnetic moment reversal under the combined action of the first write current and the pulsed magnetic field to achieve write storage of 0 and 1; and

in a read operation, under the action of the second read current, the inductor coil generates a magnetic flux coupled to the nano-superconducting quantum interference device, and the nano-wire superconducting quantum interference device switches between a superconducting state and a normal state under the action of the first read current, the magnetic flux coupled to the nano-superconducting quantum interference device generated by the induction coil under the action of the second read current, and a magnetic flux for a magnetic moment of the spin moment transfer device coupled to the nano-superconducting quantum interference device, to achieve read-out of 0 and 1.

5. The cryogenic memory cell according to claim 4 , wherein the spin moment transfer device comprises a fixed magnet-containing layer, a metal layer and a free magnetic layer stacked together, the fixed magnet-containing layer is configured to convert the first write current into a spin polarization current, and the free magnetic layer changes its magnetic polarization direction when the spin polarization current flows therethrough to achieve write storage of 0 and 1.

6. The cryogenic memory cell according to claim 4 , wherein a magnetic flux that is generated by a magnetic moment of the free magnetic layer and coupled to the nano-superconducting quantum interference device is φ1=αm, and a magnetic flux that is generated by a magnetic moment of the fixed magnet-containing layer and coupled to the nano-superconducting quantum interference device is φ2=αm′, where m is the magnetic moment of the free magnetic layer, m′ is the magnetic moment of the fixed magnet-containing layer, and α is a coupling coefficient for the coupling between the magnetic moment of the spin moment transfer device and the nano-superconducting quantum interference device, and a magnetic flux that is generated by the second read current through the inductor coil and coupled to the nano-superconducting quantum interference device is φ3=LMRxIread_X, wherein LMR is a coupling coefficient for the coupling between the inductor coil and the nano-superconducting quantum interference device, and Iread_X is the second read current; when the first read current is close to a critical current of the nano-superconducting quantum interference device, the readout signal periodically changes, one period of the periodic change of the readout signal is denoted as a flux quantum φ0; and when the conditions are satisfied: φ=LMRxIread_X+αm′=φ0/2, and αm >δφ, the nano-superconducting quantum interference device switches between the superconducting state and the normal state and achieves read-out of 0 and 1, where φ is a flux variable of the conversion between the superconducting state and the normal state of the nano-superconducting quantum interference device when the following conditions are met, and δφ is a width of the conversion between the superconducting state and the normal state of the nano-superconducting quantum interference device when the following conditions are met.

7. The cryogenic memory cell according to claim 4 , wherein the spin moment transfer device has a resistance ranging from 1 ohm to 10 ohm, and the nano-superconducting quantum interference device has a feature size of less than or equal to 100 nm.

8. A memory device, comprising:

a plurality of cryogenic memory cells of claim 1 , wherein the plurality of cryogenic memory cells is arranged at intervals in multiple rows and multiple columns;

a data writing RSFQ control circuit, which successively connects first input terminals of the cryogenic memory cells located in a same column in series;

an address compiling RSFQ control circuit, which successively connects second input terminals of the cryogenic memory cells located in a same row in series; and

a data readout RSFQ control circuit, which successively connects input/output terminals of the cryogenic memory cells located in a same column in series, wherein

ground terminals of the cryogenic memory cells are all grounded.

9. The memory device according to claim 8 , wherein the plurality of the cryogenic memory cells are arranged at intervals in N rows and M columns; the data writing RSFQ control circuit successively connects first input terminals of the cryogenic memory cells located in a same column of the M columns in series, respectively, via M connecting lines; the address compiling RSFQ control circuit successively connects second input terminals of the cryogenic memory cells located in a same row of the N rows in series, respectively, via N connecting lines; and the data readout RSFQ control circuit successively connects input/output terminals of the cryogenic memory cells located in a same column of the columns in series, respectively, via M connecting lines, where M and N are both integers greater than 1.