Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device
Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.
1. A non-volatile memory device comprising:
a memory array, the memory array including a plurality of non-volatile memory cells connected by word lines and bit lines; and
page buffer circuitry coupled to the bit lines in the memory array, a first portion of the page buffer circuitry to receive power from a first power domain and a second portion of the page buffer circuitry to receive power from a second power domain, a first voltage for the first power domain greater than a second voltage for the second power domain,
wherein the non-volatile memory cells are Three Dimensional (3D) NAND cells.
2. The non-volatile memory device of claim 1 , wherein the page buffer circuitry includes bit line driving circuitry, a sense amplifier latch and latches, the bit line driving circuitry to receive power from the first power domain and the sense amplifier latch and latches to receive power from the second power domain.
3. The non-volatile memory device of claim 2 , wherein the bit line driving circuitry includes a pre-charge PMOS transistor to pre-charge a bit line node to the first voltage.
4. The non-volatile memory device of claim 2 , wherein the bit line driving circuitry includes an inhibit path PMOS transistor, a threshold voltage of the inhibit path PMOS transistor selected via an implant process.
5. The non-volatile memory device of claim 1 , wherein the page buffer circuitry includes bit line driving circuitry, a sense amplifier latch, page buffer elaboration circuitry and latches, the latches to receive power from the first power domain and the bit line driving circuitry, the sense amplifier latch and the page buffer elaboration circuitry to receive power from the second power domain.
6. The non-volatile memory device of claim 1 , wherein the first voltage is 2.3V and the second voltage is 1.6V or 1V.
7. A system comprising:
a memory controller; and
a non-volatile memory device coupled with the memory controller, the non-volatile memory device comprising:
a memory array, the memory array including a plurality of non-volatile memory cells connected by word lines and bit lines; and
page buffer circuitry coupled to the bit lines in the memory array, a first portion of the page buffer circuitry to receive power from a first power domain and a second portion of the page buffer circuitry to receive power from a second power domain, a first voltage for the first power domain greater than a second voltage for the second power domain,
wherein the page buffer circuitry includes bit line driving circuitry, a sense amplifier latch and latches, the bit line driving circuitry to receive power from the first power domain and the sense amplifier latch and latches to receive power from the second power domain.
8. The system of claim 7 , wherein the bit line driving circuitry includes a pre-charge PMOS transistor to pre-charge a bit line node to the first voltage.
9. The system of claim 7 , wherein the bit line driving circuitry includes an inhibit path PMOS transistor, a threshold voltage of the inhibit path PMOS transistor selected via an implant process.
10. The system of claim 7 , wherein the page buffer circuitry includes bit line driving circuitry, a sense amplifier latch, page buffer elaboration circuitry and latches, the latches to receive power from the first power domain and the bit line driving circuitry, the sense amplifier latch and the page buffer elaboration circuitry to receive power from the second power domain.
11. The system of claim 7 , wherein the non-volatile memory cells are Three Dimensional (3D) NAND cells.
12. The system of claim 7 , further comprising:
one or more of:
a processor,
a power supply, and
a display coupled with the non-volatile memory device.
13. A method comprising:
receiving, by a first portion of page buffer circuitry, power from a first power domain, the page buffer circuitry coupled to a memory array, the memory array including a plurality of non-volatile memory cells connected by word lines and bit lines; and
receiving, by a second portion of the page buffer circuitry, power from a second power domain, a first voltage for the first power domain greater than a second voltage for the second power domain,
wherein the non-volatile memory cells are Three Dimensional (3D) NAND cells.
14. The method of claim 13 , wherein the page buffer circuitry includes bit line driving circuitry, a sense amplifier latch and latches, the bit line driving circuitry to receive power from the first power domain and the sense amplifier latch and latches to receive power from the second power domain.
15. The method of claim 14 , wherein the bit line driving circuitry includes a pre-charge PMOS transistor to pre-charge a bit line node to the first voltage.
16. The method of claim 14 , wherein the bit line driving circuitry includes an inhibit path PMOS transistor, a threshold voltage of the inhibit path PMOS transistor selected via an implant process.
17. The method of claim 13 , wherein the page buffer circuitry includes bit line driving circuitry, a sense amplifier latch, page buffer elaboration circuitry and latches, the latches to receive power from the first power domain and the bit line driving circuitry, the sense amplifier latch and the page buffer elaboration circuitry to receive power from the second power domain.