IP Library › Granted Patent US 12,315,828
Granted Patent B2
US 12,315,828 · App. 17/589,720 · Granted May 27, 2025

Package substrate, electronic device package and method for manufacturing the same

Inventors: Wu Chou Hsu (Kaohsiung, TW); Chih-Cheng Lee (Kaohsiung, TW); Min-Yao Chen (Kaohsiung, TW); Hsing Kuo Tien (Kaohsiung, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H01L23/645H01L21/4853H01L21/4857H01L21/565H01L23/3128H01L23/5383H01L23/5386H01L23/5389H01L24/16H01L2224/16227H01L2924/19042H01L2924/19103
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,315,828
App. No.
17/589,720
Granted
May 27, 2025
Kind
B2
Abstract

The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.

Claims (30)

1. An electronic component, comprising:

a magnetic layer; and

a conductive wire comprising a first section embedded in the magnetic layer, and a second section exposed from the magnetic layer,

wherein the first section includes a side surface exposed from the second section.

2. The electronic component of claim 1 , further comprising a second conductive wire having a third section embedded in the magnetic layer and a fourth section exposed from the magnetic layer.

3. The electronic component of claim 2 , wherein the second section and the fourth section are aligned along a same direction.

4. The electronic component of claim 1 , wherein the side surface of the first section is covered by a dielectric layer.

5. The electronic component of claim 1 , wherein the magnetic layer includes a recess disposed in an upper surface of the magnetic layer thereof and exposing the second section of the conductive wire.

6. The electronic component of claim 5 , wherein a dielectric layer fills the recess.

7. The electronic component of claim 5 , wherein a bottom surface of the recess is defined by the second section of the conductive wire.

8. The electronic component of claim 5 , wherein the bottom surface of the recess is collectively defined by the second section of the conductive wire and the magnetic layer.

9. The electronic component of claim 5 , wherein the recess includes a recessed portion recessed inward from a top surface of the conductive wire.

10. An electronic component, comprising:

a magnetic layer; and

a conductive wire comprising a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section,

wherein a first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface.

11. The electronic component of claim 10 , wherein the magnetic layer includes a first recess in an upper surface of the magnetic layer and exposing the second upper surface of the second section.

12. The electronic component of claim 10 , wherein the second upper surface of the second section is a bottom portion recessed from the first upper surface of the first section.

13. The electronic component of claim 10 , wherein the conductive wire further comprising a side surface extends from the second upper surface of the second section to the first upper surface of the first section, wherein the side surface is aligned with a side surface of the magnetic layer.

14. A package substrate, comprising:

a substrate including a first surface and a second surface opposite to the first surface;

an electronic component disposed in the substrate, the electronic component comprising:

a magnetic layer including an upper surface adjacent to the first surface and a lower surface adjacent to the second surface; and

a conductive wire comprising a first section embedded in the magnetic layer and a second section connected to the first section and exposed from the upper surface of the magnetic layer; and

a first conductive trace extending into the magnetic layer and electrically connected to the second section of the conductive wire; and

a dielectric layer disposed over the magnetic layer, wherein a top surface of the dielectric layer is aligned with a top surface of the magnetic layer.

15. The package substrate of claim 14 , wherein the dielectric layer is disposed between the magnetic layer and the first conductive trace.

16. The package substrate of claim 15 , wherein the dielectric layer encapsulates the first conductive trace.

17. The package substrate of claim 15 , wherein the dielectric layer extends in the magnetic layer.

18. The package substrate of claim 15 , wherein the dielectric layer is disposed between the magnetic layer and the substrate.

Continuity (2)
Continuation 16899507 · Jun 11, 2020
Related Publication 20220157745A1 · May 19, 2022
References Cited (5)
US 7687283B2 · Terui · 2010 [cited by applicant]
US 10145906B2 · O'Donnell et al. · 2018 [cited by applicant]
US 11239184B2 · Hsu · 2022 [cited by examiner]
US 20210104475A1 · Radhakrishnan · 2021 [cited by examiner]
Notice of Allowance for U.S. Appl. No. 16/899,507, issued Sep. 23, 2021, 9 pages. [cited by applicant]