Semiconductor memory device
A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.
1. A device comprising:
a substrate;
a memory cell provided above the substrate in a first direction; and
a bit line electrically coupled between the memory cell and the substrate, the bit line including:
a first conductor provided between the memory cell and the substrate, the first conductor extending in a second direction intersecting the first direction, and
a second conductor provided between the first conductor and the memory cell, the second conductor extending in a third direction intersecting the first direction and the second direction.
2. The device of claim 1 , further comprising:
a bonding pad provided between the substrate and the memory cell.
3. The device of claim 2 , further comprising:
a first chip; and
a second chip bonded with the first chip above the first chip in the first direction,
wherein:
the substrate is formed in the first chip, and
the memory cell, the bonding pad, and the bit line are formed in the second chip.
4. The device of claim 2 , wherein:
the substrate is formed in a first layer,
the bonding pad is formed in a second layer above the first layer in the first direction,
the bit line is formed in a third layer above the second layer in the first direction, and
the memory cell is formed in a fourth layer above the third layer in the first direction.
5. The device of claim 1 , further comprising:
another memory cell provided above the first conductor of the bit line in the first direction, the another memory cell being not electrically connected to the first conductor of the bit line.
6. The device of claim 1 , further comprising:
another memory cell electrically coupled to the second conductor of the bit line, the another memory cell being adjacent to the memory cell in the third direction.
7. The device of claim 1 , further comprising:
a transistor provided on the substrate, the transistor being electrically coupled to the bit line.
8. The device of claim 7 , further comprising:
another memory cell provided above the transistor in the first direction, the another memory cell being not electrically connected to the first conductor of the bit line.
9. The device of claim 7 , further comprising:
another transistor provided on the substrate, the first conductor of the bit line being disposed above the another transistor in the first direction.
10. The device of claim 9 , further comprising:
a word line extending in the second direction, the word line being electrically coupled to the another transistor.
11. The device of claim 10 , further comprising:
a pillar extending in the first direction, the pillar having a portion facing the word line and functioning as the memory cell.
12. The device of claim 9 , further comprising:
a sense amplifier including the transistor; and
a row decoder including the another transistor,
wherein the transistor is an n-type high breakdown voltage transistor, and the another transistor is an n-type high breakdown voltage transistor.
13. A device comprising:
a substrate;
a set of memory cells provided above the substrate in a first direction, the set of memory cells including a memory cell;
a bonding pad provided between the substrate and the memory cell; and
a bit line electrically coupled between the memory cell and the bonding pad,
the bit line including:
a first conductor provided between the memory cell and the bonding pad, the first conductor extending in a second direction intersecting the first direction, and
a second conductor provided between the first conductor and the memory cell, the second conductor extending in a third direction intersecting the first direction and the second direction.
14. The device of claim 13 , further comprising:
another memory cell provided above the first conductor of the bit line in the first direction, the another memory cell being not electrically connected to the first conductor of the bit line.
15. The device of claim 13 , further comprising:
another memory cell electrically coupled to the second conductor of the bit line, the another memory cell being adjacent to the memory cell in the third direction.
16. The device of claim 13 , further comprising:
a transistor provided on the substrate, the transistor being electrically coupled to the bit line through the bonding pad.
17. The device of claim 16 , further comprising:
another memory cell provided above the transistor in the first direction, the another memory cell being electrically disconnected from the first conductor of the bit line.
18. The device of claim 16 , further comprising:
another transistor provided on the substrate, the first conductor of the bit line being disposed above the another transistor in the first direction.
19. The device of claim 18 , further comprising:
a word line extending in the second direction, the word line being electrically coupled to the another transistor.
20. The device of claim 19 , further comprising:
a pillar extending in the first direction, the pillar having a portion facing the word line and functioning as the memory cell.