IP Library Granted Patent US 12,316,092
Granted Patent B2
US 12,316,092 · App. 17/989,611 · Granted May 27, 2025

Circuit system and manufacturing and operating method therefor

Inventors: Yan-Cun Li (Zhuhai, CN); Yi Sun (Zhuhai, CN)
Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
H02H3/10H02H1/0007H02H5/04
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Quick Facts
Patent No.
US 12,316,092
App. No.
17/989,611
Granted
May 27, 2025
Kind
B2
Abstract

A circuit system includes a power circuit and an operation circuit. The operation circuit is electrically connected to the power circuit. The operation circuit is configured to control operation of the power circuit, detect a first signal of the power circuit during the operation, and protect the power circuit in response to the first signal.

Claims (44)

1. A circuit system, comprising:

a power circuit comprising a first switch transistor; and

an operation circuit, electrically connected to the power circuit and configured to control operation of the power circuit, detect a first signal of the power circuit during the operation, and protect the power circuit in response to the first signal;

wherein the operation circuit comprises:

a second switch transistor;

a gate driver, configured to drive the second switch transistor;

a detection circuit, configured to detect the first signal flowing through the first switch transistor, wherein the detection circuit comprises a current mirror circuit configured to generate a second signal in proportion to the first signal; and

an overcurrent protection circuit, configured to receive the second signal and generate a third signal to the gate driver according to the second signal to turn off the second switch transistor;

wherein the overcurrent protection circuit comprises:

a plurality of comparators, each non-inverting input terminal of the plurality of comparators is configured to receive the second signal; and

a logic gate, configured to generate a third signal according to outputs of the plurality of comparators.

2. The circuit system according to claim 1 , wherein the first switch transistor comprising:

a substrate;

a first nitride semiconductor layer, arranged on the substrate; and

a second nitride semiconductor layer, arranged on the first nitride semiconductor layer, a band gap of the second nitride semiconductor layer being larger than a band gap of the first nitride semiconductor layer.

3. The circuit system according to claim 1 , wherein the gate driver is electrically connected to a gate of the second switch transistor, and a drain of the second switch transistor is electrically connected to a source of the first switch transistor.

4. The circuit system according to claim 3 , wherein the operation circuit comprises:

an overtemperature protection circuit, configured to turn off the second switch transistor when a temperature of the second switch transistor is too high.

5. The circuit system according to claim 4 , wherein the overtemperature protection circuit comprises a thermistor defined with a negative temperature coefficient.

6. The circuit system according to claim 3 , wherein the operation circuit comprises:

an overvoltage protection circuit, configured to turn off the second switch transistor when a voltage of the second switch transistor is too high.

7. The circuit system according to claim 6 , wherein the overvoltage protection circuit comprises:

a first resistor;

a second resistor, connected in series with the first resistor and configured to detect a partial voltage; and

a voltage comparator, having a non-inverting input terminal configured to receive the partial voltage and turn off the second switch transistor when the voltage of the second switch transistor is too high.

8. The circuit system according to claim 1 , wherein an operating voltage of the first switch transistor is greater than an operating voltage of the second switch transistor.

9. The circuit system according to claim 1 , wherein the power circuit comprises a plurality of first switch transistors, drains of the plurality of first switch transistors being electrically connected to each other, and sources of the plurality of first switch transistors being electrically connected to each other.

10. The circuit system according to claim 1 , wherein the power circuit and the operation circuit are packaged separately.

11. The circuit system according to claim 1 , wherein the power circuit and the operation circuit are packaged together.

12. A circuit system, comprising:

a first power circuit, comprising a plurality of first switch transistors, the plurality of first switch transistors being connected in parallel; and

an operation circuit, electrically connected to the first power circuit and configured to control the plurality of first switch transistors, an operating voltage of the operation circuit being less than an operating voltage of the plurality of first switch transistors;

wherein the operation circuit comprises:

a third switch transistor;

a gate driver, configured to drive the third switch transistor;

a detection circuit, configured to detect a first signal flowing through the first switch transistor, wherein the detection circuit comprises a current mirror circuit configured to generate a second signal in proportion to the first signal; and

an overcurrent protection circuit, configured to receive the second signal and generate a third signal to the gate driver according to the second signal to turn off the third switch transistor;

wherein the overcurrent protection circuit comprises:

a plurality of comparators, each non-inverting input terminal of the plurality of comparators is configured to receive the second signal; and

a logic gate, configured to generate a third signal according to outputs of the plurality of comparators.

13. The circuit system according to claim 12 , comprising:

a second power circuit, comprising a plurality of second switch transistors, the plurality of second switch transistors being connected in parallel, and the operation circuit being configured to control the plurality of second switch transistors.

14. The circuit system according to claim 13 , wherein the first power circuit, the second power circuit, and the operation circuit are packaged separately.

15. The circuit system according to claim 12 , wherein each of the plurality of first switch transistors comprises a GaN transistor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2023
From: INNOSCIENCE AMERICA, INC.
To: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
Reel/Frame 062667/0882 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2023
From: SUN, YI
To: INNOSCIENCE AMERICA, INC.
Reel/Frame 062593/0664 →
EMPLOYMENT AGREEMENT Recorded Feb 6, 2023
From: LI, YAN-CUN
To: INNOSCIENCE AMERICA, INC.
Reel/Frame 062640/0148 →
Continuity (1)
Related Publication 20240170943A1 · May 23, 2024
References Cited (6)
US 20140321012A1 · Nakayama · 2014 [cited by examiner]
US 20200021284A1 · Thalheim · 2020 [cited by examiner]
US 20220376490A1 · Sheng · 2022 [cited by examiner]
US 20230208129A1 · Liu · 2023 [cited by examiner]
US 20240204058A1 · Zhao · 2024 [cited by examiner]
US 20240304630A1 · Yamagiwa · 2024 [cited by examiner]