IP Library Granted Patent US 12,317,441
Granted Patent B2
US 12,317,441 · App. 18/417,889 · Granted May 27, 2025

Computer system and method of connecting rack-level devices

Inventors: Casey Glenn Thielen (Chandler, AZ); Eric Richard Borch (Fort Collins, CO)
Assignee: Samsung Electronics Co., Ltd.
H05K7/026
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Quick Facts
Patent No.
US 12,317,441
App. No.
18/417,889
Granted
May 27, 2025
Kind
B2
Abstract

A computer supernode including two or more printed circuit boards that each include two or more compute nodes, two or more switches, and two or more connectors. The compute nodes are connected to each switch, and the switches are connected to each connector by a number of lanes. The computer supernode also includes two or more H-cables connecting the printed circuit boards together in an all-to-all configuration. Each H-cable connects a connector of a printed circuit board to a connector in each of two or more other printed circuit boards.

Claims (40)

1. A computer supernode comprising:

a plurality of printed circuit boards, each printed circuit board of the plurality of printed circuit boards comprising:

a plurality of compute nodes;

a plurality of switches; and

a plurality of connectors,

wherein the plurality of compute nodes is connected to each switch of the plurality of switches, and

wherein the plurality of switches is connected to each connector of the plurality of connectors by a plurality of lanes; and

a plurality of H-cables connecting the plurality of printed circuit boards together in an all-to-all configuration, wherein each H-cable of the plurality of H-cables connects a connector of a first printed circuit board of the plurality of printed circuit boards to a connector in each of two or more other printed circuit boards of the plurality of printed circuit boards.

2. The computer supernode of claim 1 , wherein the plurality of printed circuit boards comprises thirty-two printed circuit boards.

3. The computer supernode of claim 2 , wherein the plurality of connectors of each printed circuit board of the plurality of printed circuit boards comprises eight connectors.

4. The computer supernode of claim 3 , wherein the plurality of H-cables is a plurality of double-H cables.

5. The computer supernode of claim 3 , wherein a number of the plurality of lanes connecting each switch of the plurality of switches to each connector of the plurality of connectors is at least four.

6. The computer supernode of claim 2 , wherein the plurality of connectors of each printed circuit board of the plurality of printed circuit boards comprises four connectors.

7. The computer supernode of claim 6 , wherein the plurality of H-cables is a plurality of quad-H cables.

8. The computer supernode of claim 6 , wherein a number of the plurality of lanes connecting each switch of the plurality of switches to each connector of the plurality of connectors is at least eight.

9. The computer supernode of claim 2 , wherein the plurality of compute nodes of each printed circuit board of the plurality of printed circuit boards comprises thirty-two compute nodes.

10. The computer supernode of claim 1 , wherein, for each printed circuit board of the plurality of printed circuit boards, the plurality of connectors is directly connected to the printed circuit board.

11. The computer supernode of claim 1 , wherein, for each printed circuit board of the plurality of printed circuit boards, the plurality of connectors is connected to the printed circuit board by cables.

12. A method of connecting a plurality of printed circuit boards together in an all-to-all configuration to form a supernode, wherein each printed circuit board of the plurality of printed circuit boards comprises a plurality of compute nodes, a plurality of switches, and a plurality of connectors, the method comprising:

connecting a first plug of a plurality of first plugs of an H-cable to a first connector of a first printed circuit board of the plurality of printed circuit boards; and

connecting a plurality of second plugs of the H-cable to a plurality of first connectors of a plurality of first printed circuit boards of the plurality of printed circuit boards,

wherein the H-cable comprises a plurality of wires connecting the first plug to the plurality of second plugs.

13. The method of claim 12 , wherein:

each printed circuit board comprises eight connectors,

the H-cable is a double-H cable,

the plurality of first plugs comprises four first plugs,

the plurality of second plugs comprises four second plugs, and

the connecting the plurality of second plugs comprises connecting the four second plugs to four printed circuit boards of the plurality of printed circuit boards.

14. The method of claim 13 , wherein the plurality of printed circuit boards comprises thirty-two circuit boards, and wherein the method further comprising connecting a second double-H cable, a third double-H cable, a fourth double-H cable, a fifth double-H cable, a sixth double-H cable, a seventh double-H cable, and an eighth double-H cable to the plurality of printed circuit boards.

15. The method of claim 12 , wherein:

each printed circuit board comprises four connectors,

the H-cable is a quad-H cable,

the plurality of first plugs comprises eight first plugs,

the plurality of second plugs comprises eight second plugs, and

the connecting the plurality of second plugs comprises connecting the eight second plugs to eight printed circuit boards of the plurality of printed circuit boards.

16. The method of claim 15 , wherein the plurality of printed circuit boards comprises thirty-two circuit boards, and wherein the method further comprising connecting a second quad-H cable, a third quad-H cable, and a fourth quad-H cable to the plurality of printed circuit boards.

17. The method of claim 12 , wherein a number of a plurality of lanes connecting each switch of the plurality of switches to each connector of the plurality of connectors is at least four.

18. The method of claim 16 , wherein a number of a plurality of lanes connecting each switch of the plurality of switches to each connector of the plurality of connectors is at least eight.

19. The method of claim 12 , wherein the plurality of compute nodes of each circuit board of the plurality of printed circuit boards comprises thirty-two compute nodes.

20. The method of claim 12 , wherein, for each printed circuit board of the plurality of printed circuit boards, the plurality of connectors is directly connected to the printed circuit board or the plurality of connectors is connected to the printed circuit board by cables.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2024
From: THIELEN, CASEY GLENN; BORCH, ERIC RICHARD
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 066539/0720 →
Continuity (2)
Provisional Application 63531376 · Aug 8, 2023
Related Publication 20250056750A1 · Feb 13, 2025
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