Semiconductor device including peripheral contact
A semiconductor device including a cell active pattern; a cell gate structure connected to the cell active pattern; a peripheral active pattern; a peripheral gate structure connected to the peripheral active pattern; a conductive pattern connected to the peripheral active pattern, the cell gate structure, or the peripheral gate structure; a capacitor structure electrically connected to the cell active pattern; an interlayer insulating layer surrounding the capacitor structure; and a peripheral contact connected to the conductive pattern while extending through the interlayer insulating layer, wherein the interlayer insulating layer includes a first material layer contacting the capacitor structure, and a second material layer on the first material layer, the peripheral contact includes a first portion contacting the first material layer, and a second portion contacting the second material layer, and a maximum width of the first portion is greater than a minimum width of the second portion.
1. A semiconductor device, comprising:
a cell active pattern;
a cell gate structure connected to the cell active pattern;
a peripheral active pattern;
a peripheral gate structure connected to the peripheral active pattern;
a conductive pattern connected to the peripheral active pattern, the cell gate structure, or the peripheral gate structure;
a capacitor structure electrically connected to the cell active pattern;
an interlayer insulating layer on the capacitor structure; and
a peripheral contact connected to the conductive pattern and extending through the interlayer insulating layer,
wherein:
the interlayer insulating layer includes a first material layer contacting the capacitor structure, and a second material layer on the first material layer, the first material layer being at a vertical level between a lowermost vertical level of the second material layer and a vertical level of the cell active pattern,
the peripheral contact includes a first portion contacting the first material layer, and a second portion contacting the second material layer, and
the maximum horizontal width of the first portion of the peripheral contact is greater than the minimum horizontal width of the second portion of the peripheral contact.
2. The semiconductor device as claimed in claim 1 , wherein a hydrogen concentration of the first material layer is higher than a hydrogen concentration of the second material layer.
3. The semiconductor device as claimed in claim 1 , wherein:
the first material layer includes hydrogen and deuterium; and
the second material layer includes hydrogen.
4. The semiconductor device as claimed in claim 1 , wherein the first material layer includes:
a sidewall horizontally between the second material layer and the capacitor structure, and
a first flat portion including a horizontal flat surface vertically between the second material layer and the conductive pattern.
5. The semiconductor device as claimed in claim 4 , wherein the first portion of the peripheral contact contacts the first flat portion of the first material layer.
6. The semiconductor device as claimed in claim 5 , wherein the first material layer further includes a second flat portion at a higher level than the second material layer.
7. The semiconductor device as claimed in claim 6 , wherein:
the interlayer insulating layer further includes a third material layer at a higher level than the second flat portion of the first material layer,
a hydrogen concentration of the first material layer is higher than a hydrogen concentration of the second material layer, and
the hydrogen concentration of the first material layer is higher than a hydrogen concentration of the third material layer.
8. The semiconductor device as claimed in claim 7 , wherein:
the peripheral contact further includes a third portion contacting the second flat portion of the first material layer, and a fourth portion contacting the third material layer; and
the maximum horizontal width of the third portion is greater than the minimum horizontal width of the fourth portion.
9. A semiconductor device, comprising:
a cell active pattern;
a cell gate structure connected to the cell active pattern;
a capacitor structure electrically connected to the cell active pattern;
an interlayer insulating layer on the capacitor structure; and
a peripheral contact extending through the interlayer insulating layer,
wherein:
the interlayer insulating layer includes a first material layer, and a second material layer having a lower hydrogen concentration than a hydrogen concentration of the first material layer,
the first material layer includes a sidewall contacting and covering an outer sidewall of the capacitor structure, and a first flat portion extending horizontally from the sidewall,
the second material layer is at a higher level than the first flat portion of the first material layer, and is on the sidewall of the first material layer,
the peripheral contact includes a first portion contacting the first flat portion of the first material layer, and a second portion contacting the second material layer, and
the maximum horizontal width of the first portion is greater than the minimum horizontal width of the second portion.
10. The semiconductor device as claimed in claim 9 , further comprising:
a conductive pattern connected to the cell gate structure; and
a wiring insulating layer covering the conductive pattern,
wherein the first flat portion of the first material layer is between the second material layer and the wiring insulating layer.
11. The semiconductor device as claimed in claim 10 , wherein:
the capacitor structure includes a lower electrode, an upper electrode, and a capacitor insulating layer; and
a portion of the capacitor insulating layer is between the first flat portion of the first material layer and the conductive pattern.
12. The semiconductor device as claimed in claim 10 , wherein the peripheral contact is connected to the conductive pattern and extends through the wiring insulating layer.
13. The semiconductor device as claimed in claim 9 , further comprising:
a peripheral active pattern; and
a peripheral gate structure connected to the peripheral active pattern,
wherein the interlayer insulating layer overlaps with the peripheral active pattern and the peripheral gate structure.
14. The semiconductor device as claimed in claim 9 , wherein a hydrogen concentration at a boundary between the first material layer and the second material layer is discontinuous.
15. A semiconductor device, comprising:
a cell active pattern;
a cell gate structure connected to the cell active pattern;
a capacitor structure electrically connected to the cell active pattern;
a first material layer including a sidewall covering an outer sidewall of the capacitor structure, and a first flat bottom portion extending horizontally from the sidewall; and
a second material layer on the sidewall of the first material layer and having a sidewall facing and contacting the sidewall of the first material layer,
wherein:
the second material layer is at a higher level than the first flat bottom portion of the first material layer, and
a hydrogen concentration of the first material layer is higher than a hydrogen concentration of the second material layer.
16. The semiconductor device as claimed in claim 15 , wherein:
the first material layer further includes a second flat portion at a higher level than the second material layer;
the second flat portion of the first material layer extends from the sidewall of the first material layer;
the semiconductor device further includes a third material layer at a higher level than the second flat portion of the first material layer; and
a hydrogen concentration of the third material layer is equal to the hydrogen concentration of the second material layer.
17. The semiconductor device as claimed in claim 16 , wherein:
the first material layer further includes a third flat portion at a higher level than the third material layer;
the third flat portion of the first material layer extends from the sidewall of the first material layer; and
a top surface of the third flat portion of the first material layer is coplanar with a top surface of the capacitor structure.
18. The semiconductor device as claimed in claim 15 , wherein:
the sidewall of the first material layer has a uniform thickness in a horizontal direction; and
the first flat bottom portion of the first material layer has a uniform thickness in a vertical direction.
19. The semiconductor device as claimed in claim 15 , wherein a top surface of the sidewall of the first material layer, a top surface of the second material layer, and a top surface of the capacitor structure are coplanar.
20. The semiconductor device as claimed in claim 15 , wherein:
the capacitor structure includes a lower electrode, an upper electrode, and a capacitor insulating layer between the lower electrode and the upper electrode; and
a bottom surface of the first flat bottom portion of the first material layer is coplanar with a bottom surface of the capacitor insulating layer.