Semiconductor switching device
A semiconductor device cell includes a drift region having a first conductivity type, a well region having a second conductivity type disposed adjacent to the drift region, the well region defining a set of well region segments. A source region having the first conductivity type is disposed adjacent to the well region and surrounded by the well region. A channel region having the second conductivity type, and defining a set of channel region segments a periphery of the channel region segment being surrounded by the well region. The well region, source region, and channel region cooperatively define a first axial length extending across the surface.
1. A semiconductor device cell having comprising:
a semiconductor layer including a drift region having a first conductivity type;
a well region having a second conductivity type disposed proximal to a surface of the semiconductor layer the well region defining a set of well region segments;
a source region having the first conductivity type disposed adjacent to the well region, a periphery of the source region surrounded by the well region;
a channel region having the second conductivity type, and proximal to the surface of the semiconductor layer, the channel region defining a set of channel region segments a periphery of the set of channel region segments being surrounded by the well region; and
wherein the well region, source region, and channel region cooperatively define a first axial length extending across the surface;
wherein a pair of immediately adjacent channel region segments are spaced apart from each other to define a gap therebetween, wherein a respective well region segment is disposed within the gap; and
wherein a portion of the channel region extends across an entire length of a periphery of the cell parallel to the first axial length.
2. The semiconductor device cell of claim 1 , further comprising a JFET region, wherein a portion of the JFET region is surrounded by the channel region.
3. The semiconductor device cell of claim 1 , wherein the gap defines a respective third axial length, orthogonal to the first axial length.
4. The semiconductor device cell of claim 3 , wherein the first axial length is within a range of 6 microns and 18 microns.
5. The semiconductor device cell of claim 4 , wherein the third axial length is within a range 0.3 microns to 1.6 microns.
6. The semiconductor device cell of claim 4 , wherein the third axial length is within the range of 8%-15% of the first axial length.
7. The semiconductor device cell of claim 1 , wherein each respective channel region segment defines a respective first longitudinal axis, and each well region segment defines a respective second longitudinal axis, wherein the first and second longitudinal axes are parallel with each other.
8. The semiconductor device cell of claim 1 , further comprising a body contact region having the second conductivity type disposed over a portion of the well region, wherein the body contact region is disposed substantially in the center of a plane of the source region defined by the surface.
9. The semiconductor device cell of claim 1 , wherein the set of channel region segments, the set of well region segments, and portions of the drift region are arranged to define a series of alternating substantially parallel bands.
10. The semiconductor device cell of claim 1 , wherein the semiconductor device cell is a MOSFET.
11. A system comprising:
a set of semiconductor device cells disposed at a surface of a silicon carbide (SiC) semiconductor layer;
wherein the set of semiconductor device cells each comprise:
a semiconductor layer including a drift region having a first conductivity type;
a well region having a second conductivity type disposed proximal to a surface of the semiconductor layer, the well region defining a set of well region segments;
a source region having the first conductivity type disposed adjacent to the well region, a periphery of the source region surrounded by the well region; and
a channel region having the second conductivity type, and proximal to the surface of the semiconductor layer, the channel region defining a set of channel region segments, a periphery of the set of channel region segment being surrounded by the well region;
wherein the well region, source region, and channel region cooperatively define a first axial length extending across the surface;
wherein a pair of immediately adjacent channel region segments are spaced apart from each other to define a gap therebetween, wherein a respective well region segment is disposed within the gap; and
wherein a portion of the channel region extends across an entire length of a periphery of the cell parallel to the first axial length.
12. The system of claim 11 , further comprising a JFET region, wherein a portion of the JFET region is surrounded by the channel region.
13. The system of claim 11 , wherein the gap defines a respective third axial length, orthogonal to the first axial length.
14. The system of claim 11 , wherein the first axial length is within a range of 6 microns and 18 microns.
15. The system of claim 13 , wherein the third axial length is within a range 0.3 microns to 1.6 microns.
16. The system of claim 13 , wherein the third axial length is within a range of 5%-20% of the first axial length.
17. The system of claim 11 , wherein each respective channel region segment defines a respective first longitudinal axis, and each well region segment defines a respective second longitudinal axis, wherein the first and second longitudinal axes are parallel with each other.
18. The system of claim 11 , further comprising a body contact region having the second conductivity type disposed over a portion of the well region, wherein the body contact region is disposed substantially in the center of a plane of the source region defined by the surface.
19. The system of claim 11 , wherein the set of channel region segments, the set of well region segments, and portions of the drift region are arranged to define a series of alternating substantially parallel bands.
20. The system of claim 11 , wherein the set of semiconductor device cells define a MOSFET.