IP Library › Granted Patent US 12,317,612
Granted Patent B2
US 12,317,612 · App. 17/620,253 · Granted May 27, 2025

Semiconductor apparatus and method for manufacturing the same

Inventors: Nobutoshi Fujii (Kanagawa, JP); Koichi Sejima (Kanagawa, JP); Koichiro Saga (Kanagawa, JP); Shinichi Miyake (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H10F39/011H01L21/31H01L21/768H10F39/18H10F39/8037H10F39/805H10F39/807H10F39/811
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,317,612
App. No.
17/620,253
Granted
May 27, 2025
Kind
B2
Abstract

An apparatus and method enabling a reduction in a resistance of a conductive path electrically connecting an upper substrate and a lower substrate. The apparatus includes a first semiconductor layer with element formation regions disposed adjacent to one another via element isolation regions, each of the element formation regions having a first active element, contact regions on an element isolation region side of a front layer portion of the element formation regions, conductive pads connected to the contact regions and extending across the element isolation region, a first insulating layer, a second semiconductor layer on the first insulating layer and having a second active element, a second insulating layer covering the second semiconductor layer, and conductive plugs extending from the second insulating layer to the conductive pad, the conductive plugs including a material identical to a material of the conductive pad and formed integrally with the conductive pad.

Claims (33)

1. A semiconductor apparatus, comprising:

a first semiconductor layer including a plurality of element formation regions disposed adjacent to one another via element isolation regions, each of the plurality of element formation regions being provided with a first active element;

contact regions each provided on a side of the element isolation region of a front layer portion of each of the plurality of element formation regions;

conductive pads connected to the contact regions of the respective plurality of element formation regions, the conductive pads extending across the element isolation region;

a first insulating layer covering the first semiconductor layer and the conductive pads;

a second semiconductor layer disposed on the first insulating layer and provided with a second active element;

a second insulating layer covering the second semiconductor layer; and

conductive plugs each embedded in a connection hole extending from the second insulating layer to a corresponding conductive pad, wherein each conductive plug includes a material that is identical to a material of the corresponding conductive pad, wherein each conductive plug is formed integrally with the corresponding conductive pad, and

wherein each conductive pad is larger in area in plan view than the corresponding conductive plug.

2. The semiconductor apparatus according to claim 1 , wherein

the conductive pad and the conductive plug each include a metal material with a high melting point.

3. The semiconductor apparatus according to claim 1 , wherein

the first active element includes a photodiode and a transfer transistor including a source region electrically connected to a cathode region of the photodiode and a drain region electrically connected to the conductive plug, and

the second active element includes an amplifying transistor including a gate electrode electrically connected to the conductive plug.

4. A method for manufacturing a semiconductor apparatus, the method comprising:

forming, in a first semiconductor layer, a plurality of element formation regions delimited by element isolation regions;

forming contact regions each on a side of the element isolation region of a front layer portion of each of the plurality of element formation regions adjacent to one another via the element isolation regions;

forming pad cores, via an etching stopper film, on the contact regions of the respective plurality of element formation regions, the pad cores extending across the element isolation regions;

forming a first active element in each of the plurality of element formation regions;

forming a first insulating layer covering the first semiconductor layer and the pad cores;

disposing a second semiconductor layer on the first insulating layer;

executing a step including thermal treatment to form a second active element in the second semiconductor layer;

forming a second insulating layer covering the second semiconductor layer;

forming connection holes each extending from the second insulating layer to the pad cores;

for each of the connection holes, removing the pad core and the etching stopper film through the connection hole to form a space portion communicating with the connection hole; and

embedding a conductive material into the space portions and the connection holes to form a conductive pad connected to the contact regions and a conductive plug integrated with the conductive pad,

wherein the conductive pads are larger in area in plan view than the conductive plugs.

5. The method for manufacturing a semiconductor apparatus, the method according to claim 4 , wherein

the pad core includes a non-doped polycrystal silicon film.

6. The method for manufacturing a semiconductor apparatus, the method according to claim 5 , wherein

the step of forming the second active element includes

a step of executing thermal treatment to form, on a front surface of the second semiconductor layer, a gate insulating film including a thermal oxide film, and

a step of executing thermal treatment to form a source region and a drain region in a front layer portion of the second semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2022
From: FUJII, NOBUTOSHI; SEJIMA, KOICHI; SAGA, KOICHIRO; MIYAKE, SHINICHI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 059543/0307 →
Priority Claims (1)
JP 2019-119169 · Jun 26, 2019 · national
Continuity (1)
Related Publication 20220367558A1 · Nov 17, 2022
References Cited (24)
US 5952724A · Horiba · 1999 [cited by applicant]
US 9620548B1 · Wang et al. · 2017 [cited by applicant]
US 10468439B2 · Ikeda · 2019 [cited by examiner]
US 10608034B2 · Endo · 2020 [cited by examiner]
US 10950650B2 · Ihara · 2021 [cited by examiner]
US 11437420B2 · Hung · 2022 [cited by examiner]
US 11502117B2 · Ha · 2022 [cited by examiner]
US 20020024093A1 · Ahn et al. · 2002 [cited by applicant]
US 20070018075A1 · Cazaux et al. · 2007 [cited by applicant]
US 20160086984A1 · Wang · 2016 [cited by examiner]
US 20170125473A1 · Wang et al. · 2017 [cited by applicant]
US 20170200763A1 · Wang et al. · 2017 [cited by applicant]
US 20170207259A1 · Yun · 2017 [cited by applicant]
US 20180090534A1 · Kim · 2018 [cited by applicant]
US 20180190694A1 · Ihara · 2018 [cited by applicant]
JP H02054554 · 1990 [cited by applicant]
JP H08008208 · 1996 [cited by applicant]
JP H10012726 · 1998 [cited by applicant]
JP 2002100685 · 2002 [cited by applicant]
JP 2014099582 · 2014 [cited by applicant]
JP 2015032687 · 2015 [cited by applicant]
JP 2016219788 · 2016 [cited by applicant]
Datta et al., “Impact of Contact and Local Interconnect Scaling on Logic Performance,” 2014 Symposium on VLSI Technology Digest of Technical Papers, Jun. 9, 2014, 2 pages. [cited by applicant]
International Search Report prepared by the Japan Patent Office on Sep. 15, 2020, for International Application No. PCT/JP2020/025147, 6 pgs. [cited by applicant]
Cited By (1)
US 12,648,249