Compressed wallace trees in FMA circuits
An embodiment of an apparatus comprises one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree, and circuitry coupled to the one or more fractional width FMA circuits to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits. Other embodiments are disclosed and claimed.
1. An apparatus, comprising:
two or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree comprising:
multiple 3:2 carry-save adder (CSA) circuits comprising a first 3:2 CSA circuit, a second 3:2 CSA circuit, and a third 3:2 CSA circuit;
a first 4:2 CSA circuit coupled to receive respective signals from the first 3:2 CSA circuit and the second 3:2 CSA circuit;
a second 4:2 CSA circuit coupled to receive respective signals from the first 4:2 CSA circuit and the third 3:2 CSA circuit; and
a multiplexer circuit coupled to selectively enable or prevent a communication of a carry signal between two of the multiple 3:2 CSA circuits; and
circuitry coupled to the two or more fractional width FMA circuits to provide one or more fractional width FMA operations through the two or more fractional width FMA circuits.
2. The apparatus of claim 1 , wherein the two or more fractional width FMA circuits support per-cycle operations of any of multiple different datatype widths.
3. The apparatus of claim 2 , wherein the two or more fractional width FMA circuits comprises:
a first set of cascaded carry-save adders (CSAs) that provide a first half-width FMA circuit; and
a second set of cascaded CSAs that provide a second half-width FMA circuit.
4. The apparatus of claim 3 , wherein the circuitry is further to:
provide two half-width FMA operations per cycle.
5. The apparatus of claim 3 , wherein the circuitry is further to:
provide half of a full width FMA operation per cycle.
6. The apparatus of claim 5 , wherein the circuitry is further to:
provide two passes through the first and second half-width FMA circuits to perform the full width FMA operation.
7. The apparatus of claim 5 , further comprising a second pair of half-width FMA circuits coupled sequentially to the first and second half-width FMA circuits, wherein the circuitry is further to:
provide the full width FMA operation per cycle in a pipelined manner through the first and second half-width FMA circuits followed by the second pair of half-width FMA circuits.
8. A method, comprising:
providing two or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree comprising:
multiple 3:2 carry-save adder (CSA) circuits comprising a first 3:2 CSA circuit, a second 3:2 CSA circuit, and a third 3:2 CSA circuit;
a first 4:2 CSA circuit coupled to receive respective signals from the first 3:2 CSA circuit and the second 3:2 CSA circuit;
a second 4:2 CSA circuit coupled to receive respective signals from the first 4:2 CSA circuit and the third 3:2 CSA circuit; and
a multiplexer circuit coupled to selectively enable or prevent a communication of a carry signal between two of the multiple 3:2 CSA circuits; and
providing one or more fractional width FMA operations through the two or more fractional width FMA circuits.
9. The method of claim 8 , wherein the two or more fractional width FMA circuits support per-cycle operations of any of multiple different datatype widths.
10. The method of claim 8 , further comprising:
providing two half-width FMA operations per cycle.
11. The method of claim 8 , further comprising:
providing half of a full width FMA operation per cycle.
12. The method of claim 11 , further comprising:
providing two passes through a first pair of half-width FMA circuits to perform a full width FMA operation.
13. The method of claim 11 , further comprising:
providing a second pair of half-width FMA circuits coupled sequentially to the first pair of half-width FMA circuits; and
providing the full width FMA operation per cycle in a pipelined manner through the first pair of half-width FMA circuits followed by the second pair of half-width FMA circuits.
14. The method of claim 8 , further comprising:
utilizing a systolic array of the one or more fractional width FMA circuits to support an associated matrix to matrix multiplication.
15. An apparatus, comprising:
a processor core;
a memory; and
a fused multiply-accumulate (FMA) unit coupled to the processor core and the memory, wherein the FMA unit comprises two or more fractional width FMA circuits configured as a shared Wallace tree comprising:
multiple 3:2 carry-save adder (CSA) circuits comprising a first 3:2 CSA circuit, a second 3:2 CSA circuit, and a third 3:2 CSA circuit;
a first 4:2 CSA circuit coupled to receive respective signals from the first 3:2 CSA circuit and the second 3:2 CSA circuit;
a second 4:2 CSA circuit coupled to receive respective signals from the first 4:2 CSA circuit and the third 3:2 CSA circuit; and
a multiplexer circuit coupled to selectively enable or prevent a communication of a carry signal between two of the multiple 3:2 CSA circuits;
wherein the FMA unit is to provide one or more fractional width FMA operations through the two or more fractional width FMA circuits.
16. The apparatus of claim 15 , wherein the two or more fractional width FMA circuits support per-cycle operations of any of multiple different datatype widths.
17. The apparatus of claim 16 , wherein the two or more fractional width FMA circuits comprises:
a first set of cascaded carry-save adders (CSAs) that provide a first half-width FMA circuit; and
a second set of cascaded CSAs that provide a second half-width FMA circuit.
18. The apparatus of claim 17 , wherein the FMA unit is further to:
provide two half-width FMA operations per cycle.
19. The apparatus of claim 17 , wherein the FMA unit is further to:
provide half of a full width FMA operation per cycle.
20. The apparatus of claim 19 , wherein the FMA unit is further to:
provide two passes through the first and second half-width FMA circuits to perform the full width FMA operation.
21. The apparatus of claim 19 , wherein the FMA unit further comprises a second pair of half-width FMA circuits coupled sequentially to the first and second half-width FMA circuits, and wherein the FMA unit is further to:
provide the full width FMA operation per cycle in a pipelined manner through the first and second half-width FMA circuits followed by the second pair of half-width FMA circuits.