IP Library Granted Patent US 12,321,798
Granted Patent B1
US 12,321,798 · App. 18/394,199 · Granted Jun 3, 2025

RFID tag clock frequency reduction during tuning

Inventors: John D. Hyde (Corvallis, OR); Shailendra Srinivas (Seattle, WA); Jay Kuhn (Seattle, WA); Ronald A Oliver (Seattle, WA); Harley Heinrich (Snohomish, WA); Theron Stanford (Seattle, WA); Christopher J. Diorio (Shoreline, WA)
Assignee: Impinj, Inc.
G06K19/0712G06K7/016G06K7/10148G06K7/10198
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Quick Facts
Patent No.
US 12,321,798
App. No.
18/394,199
Granted
Jun 3, 2025
Kind
B1
Abstract

An RFID IC may operate at a relatively low clock frequency while impedance matching to an antenna is being tuned to increase the amount of power that the IC can extract from an incident RF wave. A tuning circuit tunes the impedance matching by adjusting a variable impedance coupling the IC and the antenna. The IC may power-up with a low clock frequency or reduce its current clock frequency to a lower clock frequency prior to tuning or during the tuning process, and may increase its clock frequency upon completion of tuning or during the tuning process.

Claims (44)

1. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:

a variable impedance; and

a tuning circuit coupled to and configured to tune the variable impedance, wherein the IC is configured to:

determine that tuning of the variable impedance is to occur;

select a first clock frequency to use for the tuning;

extract a first power from an RF wave insufficient for the IC to fully operate;

cause the tuning circuit to tune, using the first clock frequency, the variable impedance to increase power extracted from the RF wave; and

after the tuning circuit tunes the variable impedance:

extract a second power from the RF wave sufficient for the IC to fully operate;

select a second clock frequency to use for IC operation; and

operate using the second clock frequency.

2. The RFID IC of claim 1 , further configured to determine that tuning of the variable impedance is to occur based on a received command.

3. The RFID IC of claim 1 , further configured to determine that tuning of the variable impedance is to occur upon determining that the extracted first power is insufficient for the IC to fully operate.

4. The RFID IC of claim 1 , further configured to determine that tuning of the variable impedance is to occur based on an IC operating state.

5. The RFID IC of claim 1 , further configured to determine that tuning of the variable impedance is to occur based on an IC power-up.

6. The RFID IC of claim 1 , wherein the first and second clock frequencies are different.

7. The RFID IC of claim 1 , wherein the first clock frequency is below a minimum clock frequency to operate according to a protocol (MFOP).

8. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:

a variable impedance; and

a tuning circuit coupled to and configured to tune the variable impedance, wherein the IC is configured to:

upon power-up, determine that tuning of the variable impedance is to occur and select a first clock frequency to use during the tuning;

extract a first power from an RF wave insufficient for the IC to operate according to a protocol;

cause the tuning circuit to tune, using the first clock frequency, the variable impedance to increase power extracted from the RF wave; and

after the tuning circuit tunes the variable impedance:

extract a second power from the RF wave higher than the first power and sufficient for the IC to operate according to the protocol;

select a second clock frequency higher than the first clock frequency to use for IC operation; and

operate using the second clock frequency.

9. The RFID IC of claim 8 , further configured to determine that tuning of the variable impedance is to occur based on a received command.

10. The RFID IC of claim 8 , further configured to determine that tuning of the variable impedance is to occur upon determining that the extracted first power is insufficient for the IC to operate according to the protocol.

11. The RFID IC of claim 8 , further configured to determine that tuning of the variable impedance is to occur based on an IC operating state.

12. The RFID IC of claim 8 , further configured to determine that tuning of the variable impedance is to occur based on the power-up.

13. The RFID IC of claim 8 , further comprising a first oscillator configured to provide the first clock frequency and a second oscillator configured to provide the second clock frequency.

14. The RFID IC of claim 8 , wherein the first clock frequency is below a minimum clock frequency to operate according to a protocol (MFOP).

15. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising:

a variable impedance; and

a tuning circuit coupled to and configured to tune the variable impedance; wherein the IC is configured to:

upon power-up, extract a first power from an RF wave and determine that tuning of the variable impedance is to occur;

while extracting the first power and operating at a first clock frequency sufficient for the tuning circuit to tune the variable impedance but insufficient for the IC to operate according to a protocol, cause the tuning circuit to tune the variable impedance to increase power extracted from the RF wave; and

after the tuning circuit tunes the variable impedance, operate at a second clock frequency different than the first clock frequency and extract a second power from the RF wave higher than the first power.

16. The RFID IC of claim 15 , further configured to determine that tuning of the variable impedance is to occur based on a received command.

17. The RFID IC of claim 15 , further configured to determine that tuning of the variable impedance is to occur based on an IC operating state.

18. The RFID IC of claim 15 , further configured to determine that tuning of the variable impedance is to occur based on the power-up.

19. The RFID IC of claim 15 , wherein the second clock frequency and the second power are sufficient for the IC to operate according to the protocol.

20. The RFID IC of claim 15 , further comprising a first oscillator configured to provide the first clock frequency and a second oscillator configured to provide the second clock frequency.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2023
From: HYDE, JOHN D.; STANFORD, THERON; HEINRICH, HARLEY; KUHN, JAY; DIORIO, CHRISTOPHER J.
To: IMPINJ, INC.
Reel/Frame 065942/0099 →
Continuity (6)
Continuation 17868504 · Jul 19, 2022
Continuation 17179546 · Feb 19, 2021
Continuation 16597866 · Oct 10, 2019
Continuation 15985054 · May 21, 2018
Continuation 14820502 · Aug 6, 2015
Provisional Application 62035305 · Aug 8, 2014
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