Resistive random access memory device
A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
1. A memory device, comprising:
a first cell array comprising a first plurality of bit cells configured to transition between logic states;
a second cell array comprising a second plurality of bit cells configured to transition between logic states; and
a control logic circuit configured to cause a first information bit to be written into at least one bit cell of the first cell array as an original logic state of the first information bit, and to cause a second information bit to be written into at least one bit cell of the second cell array as an original logic state of the second information bit, wherein the first plurality of bit cells has a first endurance, and the second plurality of bit cells has a second endurance that is different from the first endurance; and
a third cell array comprising a third plurality of bit cells, wherein the control circuit is further configured to cause a logically complementary state of the first information bit to be stored in respective bit cells of the third cell array.
2. The memory device of claim 1 , wherein:
the first plurality of bit cells use a first variable resistance dielectric layer to transition between logic states,
the second plurality of bit cells use a second variable resistance dielectric layer to transition between logic states, and
the first and second variable resistance dielectric layers are formed based on a same recipe of deposition equipment, and share substantially an identical thickness and/or crystalline structure.
3. The memory device of claim 2 , wherein:
the first variable resistance dielectric layer has a first diameter,
the second variable resistance dielectric layer has a second diameter, and
the first diameter is smaller than the second diameter.
4. The memory device of claim 1 , further comprising:
a sensing circuit, coupled to the first, second and third pluralities of bit cells, and configured to determine the first information bit's original logic state present by the respective bit cells of the first and third cell arrays by comparing respective current signals conducting through the respective bit cells of the first and third cell arrays.
5. The memory device of claim 4 , wherein the sensing circuit is further configured to determine the second information bit's original logic state present by the at least one bit cell of the second cell array by comparing a current signal conducting through the at least one bit cell of the second cell array with a reference current signal.
6. The memory device of claim 1 , wherein:
each of the first and second pluralities of bit cells comprises a resistive random access memory (RRAM) bit cell; and
the first and second cell arrays are formed as a memory macro disposed on a single chip.
7. A memory device, comprising:
a first cell array comprising a first plurality of bit cells;
a second cell array comprising a second plurality of bit cells;
a third cell array comprising a third plurality of bit cells;
a control logic circuit configured to cause a first information bit to be written into at least one bit cell of the first cell array as an original logic state of the first information bit, cause a logically complementary state of the first information bit to be stored in at least one bit cell of the third cell array, and cause a second information bit to be written into at least one bit cell of the second cell array as an original logic state of the second information bit, such that the respective at least one bit cells of the first and third cell arrays have a first endurance and the at least one bit cell of the second cell array has a second endurance; and
a sensing circuit, coupled to the first, second and third pluralities of bit cells, and configured to determine the first information bit's original logic state present by the respective at least one bit cells of the first and third cell arrays by comparing respective current signals conducting through the respective at least one bit cells of the first and third cell arrays.
8. The memory device of claim 7 , wherein:
the first endurance comprises a maximum number of cycles for which the respective bit cells of the first cell array can transition between respective different resistance states; and
the second endurance comprises a maximum number of cycles for which the bit cell of the second cell array can transition between respective different resistance states.
9. The memory device of claim 7 , wherein the first endurance is substantially higher than the second endurance.
10. The memory device of claim 7 , wherein:
the first plurality of bit cells uses a first variable resistance dielectric layer to transition between logic states,
the second plurality of bit cells uses a second variable resistance dielectric layer to transition between logic states, and
the first variable resistance dielectric layer has a first diameter,
the second variable resistance dielectric layer has a second diameter different from the first diameter.
11. The memory device of claim 10 , wherein:
the third plurality of bit cells uses a third variable resistance dielectric layer to transition between logic states, and
the third variable resistance dielectric layer has the first diameter.
12. The memory device of claim 7 , wherein the first and third cell arrays are disposed at respective opposite sides of the sensing circuit.
13. The memory device of claim 7 , wherein the sensing circuit is further configured to read out the original logic state of the second information bit present by the at least one bit cell of the second cell array by comparing a current signal conducting through the at least one bit cell of the second cell array with a reference current signal.
14. The memory device of claim 7 , wherein each of the first, second, and third pluralities of bit cells comprises a resistive random access memory (RRAM) bit cell.
15. The memory device of claim 7 , wherein:
the first, second, and third cell arrays are formed as a memory macro disposed on a single chip; and
the first, second, and third pluralities of bit cells have respective variable resistance dielectric layers that are formed by a same recipe of deposition equipment but have different diameters.
16. A method, comprising:
causing a first plurality of bit cells using a first variable resistance dielectric layer to transition between logic states;
causing a second plurality of bit cells using a second variable resistance dielectric layer to transition between logic states;
causing a first information bit to be written into at least one bit cell of the first plurality of bit cells as an original logic state of the first information bit; and
causing a second information bit to be written into at least one bit cell of the second plurality of bit cells as an original logic state of the second information bit,
wherein the first and second variable resistance dielectric layers are formed based on a same recipe of deposition equipment, and have different diameters.
17. The method of claim 16 , wherein:
the first variable resistance dielectric layer has a first diameter;
the second variable resistance dielectric layer has a second diameter; and
the first diameter is smaller than the second diameter.
18. The method of claim 16 , further comprising:
causing a logically complementary state of the first information bit to be stored in at least bit cell of a third plurality of bit cells; and
determining the first information bit's original logic state present by comparing respective current signals conducting through the respective at least one bit cells of the first and third plurality of bit cells.
19. The method of claim 18 , wherein:
the first plurality of bit cells form a first cell array;
the second plurality of bit cells form a second cell array;
the third plurality of bit cells form a third cell array;
the first and third cell arrays are disposed at respective opposite sides of the sensing circuit; and
the sensing circuit is further configured to determine the second information bit's original logic state present by the single bit cell of the second cell array by comparing a current signal conducting through the single bit cell of the second cell array with a reference current signal.
20. The method of claim 19 , wherein:
each of the first, second and third pluralities of bit cells comprises a resistive random access memory (RRAM) bit cell; and
the first, second and third cell arrays are formed as a memory macro disposed on a single chip.