Efficient staggered multi-tone (SMT) modulation/demodulation with time-domain phase adjustment
A staggered multi-tone (SMT) modulator that includes a Fourier transform module that is coupled to an input for receiving a complex valued data frame and that transforms the complex valued data frame from a frequency domain into a time domain. A symmetry extractor module extracts a conjugate symmetric data frame and a conjugate antisymmetric data frame from the transformed complex data frame. A first circular shift module performs a circular rotational phase shift on the conjugate symmetric data frame. A first filter filters the phase shifted conjugate symmetric data frame. A second circular shift module performs a circular rotational phase shift on the conjugate antisymmetric data frame. A second filter filters the phase shifted conjugate antisymmetric data frame. A summing module sums the phase shifted conjugate symmetric data frame and the phase shifted conjugate antisymmetric data frame to generate a modulated data frame.
1. A staggered multi-tone (SMT) modulator comprising:
a Fourier transform module that is coupled to an input for receiving a complex valued data frame, the Fourier transform module configured to transform the complex valued data frame from a frequency domain into a time domain;
a symmetry extractor module configured to extract a conjugate symmetric data frame and a conjugate antisymmetric data frame from the transformed complex data frame;
a first circular shift module configured to perform a circular rotational phase shift on the conjugate symmetric data frame;
a first filter configured to filter the phase shifted conjugate symmetric data frame;
a second circular shift module configured to perform a circular rotational phase shift on the conjugate antisymmetric data frame;
a second filter configured to filter the phase shifted conjugate antisymmetric data frame; and
a summing module configured to sum the phase shifted conjugate symmetric data frame and the phase shifted conjugate antisymmetric data frame to generate a modulated data frame for an output that is coupled to the summing module.
2. The computing system of claim 1 , further comprising:
a time delay module coupled to either the first or second filter, the time delay module providing a time delay of one-half of a data frame.
3. The computing system of claim 2 , wherein the time delay module is at least partially distributed across one or more elements of the SMT modulator.
4. The computing system of claim 1 , wherein the first and second filter modules comprise one or more polyphase filters.
5. The computing system of claim 1 , wherein the Fourier transform module is implemented as a Fast Fourier Transform (FFT).
6. The computing system of claim 1 , wherein the Fourier transform module is implemented as an Inverse Fast Fourier Transform (IFFT).
7. The computing system of claim 1 , wherein because the conjugate symmetric data frame and the conjugate antisymmetric data frame are subjected to the circular rotational phase shift in the time domain, no linear phase modulation in the frequency domain is performed by the SMT modulator.
8. The computing system of claim 1 , wherein the SMT modulator is configured to be used in a digital transmitter.
9. The computing system of claim 1 , wherein the SMT modulator is instantiated in an Application Specific Integrated Circuit (ASIC) or in a Field Programable Gate Array (FPGA).
10. The computing system of claim 1 , wherein the SMT modulator is implemented in a computing system that includes one or more processors and one or more computer-readable hardware storage devices having stored thereon computer-executable instructions that are structured such that when executed by the one or more processors, cause the computing system to instantiate the SMT modulator.
11. A staggered multi-tone (SMT) demodulator comprising:
a filter configured to filter a complex valued data frame received from a demodulator input to generate a phase one filtered data frame and a phase two filtered data frame;
a first circular shift module configured to perform a circular rotational phase shift on the phase one filtered data frame;
a second circular shift module configured to perform a circular rotational phase shift on the phase two filtered data frame;
a symmetry extractor module configured to extract a conjugate symmetric data frame from the phase one filtered data frame and to extract a conjugate antisymmetric data frame from the phase two filtered data frame;
a summing module configured to sum the conjugate symmetric data frame and the conjugate antisymmetric data frame to generate a summed data frame; and
a Fourier transform module configured to transform the summed data frame from a time domain to a frequency domain to generate a demodulated data frame for an output that is coupled to the Fourier transform module.
12. The computing system of claim 11 , further comprising:
a time delay module coupled to the filter, the time delay module providing a time delay of one-half of a data frame.
13. The computing system of claim 12 , wherein the time delay module is at least partially distributed across one or more elements of the SMT demodulator.
14. The computing system of claim 11 , wherein the filter module comprises one or more polyphase filters.
15. The computing system of claim 14 , wherein the filter module comprises a first filter module and a second filter module.
16. The computing system of claim 11 , wherein the Fourier transform module is implemented as one of a Fast Fourier Transform (FFT) or an Inverse Fast Fourier Transform (IFFT).
17. The computing system of claim 11 , wherein because the phase one filtered data frame and the phase two filtered data frame are subjected to the circular rotational phase shift in the time domain, no linear phase modulation in the frequency domain is performed by the SMT demodulator.
18. The computing system of claim 11 , wherein the SMT demodulator is configure to be used in a digital receiver.
19. The computing system of claim 11 , wherein the SMT demodulator is instantiated m an Application Specific Integrated Circuit (ASIC) or in a Field Programable Gate Array (FPGA).
20. The computing system of claim 11 , wherein the SMT modulator is implemented in a computing system that includes one or more processors and one or more computer-readable hardware storage devices having stored thereon computer-executable instructions that are structured such that, when executed by the one or more processors, cause the computing system to instantiate the SMT demodulator.