Stacked capacitors with shared electrodes and methods of fabrication
A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.
1. A method of fabricating a device structure, the method comprising:
fabricating a plurality of transistors within a first level, wherein individual ones of the plurality of transistors comprise a source, a drain, and a gate between the source and the drain, a drain contact coupled with the drain and a gate contact coupled with the gate;
forming a bridge structure connected between the gate contact of a first transistor in the plurality of transistors to the drain contact of a second transistor in the plurality of transistors;
forming an electrode structure by forming an opening in an etch stop layer deposited above the bridge structure and by filling the opening with a conductive material, wherein the electrode structure is coupled with the bridge structure;
depositing an electrode layer on the electrode structure;
forming a first plurality of memory devices on the electrode layer by depositing a material layer stack comprising a ferroelectric material or a paraelectric material;
etching the electrode layer to form a first plate electrode;
forming a signal electrode on the first plate electrode, wherein the signal electrode is formed between a pair of memory devices of the individual ones of the first plurality of memory devices;
forming a second plate electrode above and coupled with the signal electrode; and
forming a second plurality of memory devices on the second plate electrode.
2. The method of claim 1 , wherein forming the first plate electrode comprises etching portions of the electrode layer to form the first plate electrode that extends beyond a perimeter of the individual ones of the plurality of transistors and the electrode structure.
3. The method of claim 1 , further comprising:
forming a first plurality of via electrodes, wherein individual ones of the first plurality of via electrodes are formed on the individual ones of the first plurality of memory devices; and
forming a second plurality of via electrodes, wherein individual ones of the second plurality of via electrodes are formed on individual ones of the second plurality of memory devices.
4. The method of claim 3 , further comprising forming a first plurality of conductive vias, wherein individual ones of the first plurality of conductive vias are formed on the individual ones of first plurality of via electrodes and on the signal electrode.
5. The method of claim 1 , wherein forming the signal electrode further comprises forming between an equal number of memory devices in the first plurality of memory devices on either side.
6. The method of claim 1 , wherein etching to form the first plurality of memory devices comprises partially recessing the electrode layer to form the electrode layer having a variable thickness.
7. The method of claim 4 , wherein immediately after forming the first plurality of conductive vias, the method further comprises:
depositing a second etch stop layer above the first plurality of conductive vias;
forming a second electrode structure coupled with an individual via electrode on the signal electrode, wherein forming the second electrode structure comprises forming a second opening in the second etch stop layer and by filling the opening with the conductive material;
planarizing to form the second electrode structure; and
depositing a material of the electrode layer on the second electrode structure.
8. The method of claim 7 , wherein the material layer stack is a first material layer stack, wherein the electrode layer is a first electrode layer, and wherein forming the second plate electrode and the second plurality of memory devices further comprises:
depositing a second electrode layer on the second electrode structure;
depositing a second material layer stack on the second electrode structure and patterning the second material layer stack to form the second plurality of memory devices; and
etching portions of the material of the second electrode layer to form the second plate electrode, wherein the second plate electrode extends beyond a perimeter of the individual ones of the plurality of transistors.
9. The method of claim 4 , wherein forming the first plurality of via electrodes further comprises: depositing a first dielectric above the first plurality of memory devices; forming a first via opening above the individual ones of the first plurality of memory devices; and depositing at least a first conductive hydrogen barrier material in the first via opening.
10. The method of claim 3 , wherein forming the second plurality of via electrodes further comprises: depositing a second dielectric above the second plurality of memory devices; forming a second via opening above the individual ones of the second plurality of memory devices; and depositing at least a second conductive hydrogen barrier material in the second via opening.
11. The method of claim 8 , further comprising: forming a first dielectric spacer adjacent to the individual ones of the first plurality of memory devices prior to etching the electrode layer; and forming a second dielectric spacer adjacent to the individual ones of the second plurality of memory devices prior to etching the second electrode layer.
12. The method of claim 9 , wherein forming the first plurality of conductive vias further comprises depositing a third dielectric on the first dielectric, wherein the third dielectric comprises a material that is different from the first dielectric.
13. The method of claim 8 , wherein depositing the first material layer stack and the second material layer stack comprises:
depositing the ferroelectric material comprising one of:
bismuth ferrite (BFO) or BFO with a first doping material wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite material which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3; a hexagonal ferroelectric which includes one of: YMnO3, or LuFeO3;
hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides; hafnium oxides as Hf (1−x) E x O y , where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, where x and y are first and second fractions, respectively;
Al (1−x) Sc (x) N, Ga (1−x) Sc (x) N, Al (1−x) Y (x) N or Al (1−x−y) Mg (x) Nb (y) N, where x and y are third and fourth fractions, respectively;
y doped HfO 2 , where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100; or
depositing the paraelectric material comprising SrTiO 3 , Ba (x) Sr (y) TiO 3 (where x is −0.05, and y is 0.95), HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or a PMN-PT based relaxor ferroelectrics.
14. A method of fabricating a system, the method comprising:
fabricating a plurality of transistors in a first level, wherein individual ones of the plurality of transistors comprise:
a source;
a drain;
a gate between the source and the drain;
a drain contact coupled with the drain; and
a gate contact coupled with the gate;
forming a bridge structure connected between the gate contact of a first transistor in the plurality of transistors to the drain contact of a second transistor in the plurality of transistors;
forming an electrode structure by forming an opening in an etch stop layer deposited above the bridge structure and by filling the opening with a conductive material,
forming a first plurality of memory devices by depositing a first material layer stack comprising a first ferroelectric material or a first paraelectric material above a first electrode layer and etching the first material layer stack;
depositing a first encapsulation layer on the first plurality of memory devices and on the first electrode layer;
forming a first plate electrode;
forming a signal electrode on the first plate electrode, wherein the signal electrode is formed between a pair of memory devices of individual ones of the first plurality of memory devices;
forming a second plurality of memory devices by depositing a second material layer stack comprising a second ferroelectric material or a second paraelectric material above a second electrode layer and etching the second material layer stack, wherein the second electrode layer is coupled with the signal electrode;
depositing a second encapsulation layer on the second plurality of memory devices and on the second electrode layer; and
forming a second plate electrode.
15. The method of claim 14 , wherein forming the first plate electrode further comprises:
forming a first mask over the first encapsulation layer; and
using the first mask to etch the first encapsulation layer and the first electrode layer to form the first plate electrode comprising a first perimeter that is substantially aligned with a second perimeter of the first encapsulation layer, wherein the first plate electrode extends beyond sidewalls of the first plurality of memory devices.
16. The method of claim 14 , wherein forming the second plate electrode further comprises:
forming a second mask over the second encapsulation layer; and
using the second mask to etch the second encapsulation layer and the second electrode layer to form the second plate electrode comprising a third perimeter that is substantially aligned with a fourth perimeter of the second encapsulation layer and wherein the second plate electrode extends beyond sidewalls of the second plurality of memory devices.
17. The method of claim 14 , wherein depositing the first encapsulation layer comprises conformally depositing a material comprising silicon nitride, carbon doped silicon nitride, Al x O y , HfO x , ZrO x , TaO x , TiO x , AlSiO x , HfSiO x , or TaSiO x on the first plurality of memory devices and on the first electrode layer, and wherein depositing the second encapsulation layer comprises conformally depositing a material comprising silicon nitride, carbon doped silicon nitride, Al x O y , HfO x , ZrO x , TaO x , TiO x , AlSiO x , HfSiO x , or TaSiO x on the second plurality of memory devices and on the second electrode layer.
18. The method of claim 14 , wherein the method comprises forming the first plurality of memory devices on a first plane, wherein the method further comprises forming a third plurality of memory devices on a second plane behind the first plane, wherein the first plurality of memory devices and the third plurality of memory devices are formed on a same level; wherein the method comprises forming the second plurality of memory devices on the first plane, and wherein the method further comprises forming a fourth plurality of memory devices on the second plane behind the first plane.
19. A method of fabricating a system, the method comprising:
fabricating a plurality of transistors in a first level, wherein individual ones of the plurality of transistors comprise:
a source;
a drain;
a gate between the source and the drain;
a drain contact coupled with the drain; and
a gate contact coupled with the gate;
forming a bridge structure connected between the gate contact of a first transistor in the plurality of transistors to the drain contact of a second transistor in the plurality of transistors;
forming a conductive interconnect in a first dielectric, wherein the conductive interconnect is coupled with the bridge structure;
depositing an etch stop layer on the first dielectric and on the conductive interconnect;
forming a first electrode structure on the conductive interconnect by a first process comprising:
etching a first opening in the etch stop layer; and
depositing a first conductive hydrogen barrier layer and a first conductive material in the first opening;
depositing a first electrode layer on the first electrode structure and on the etch stop layer;
forming a first plurality of memory devices by depositing a first material layer stack comprising a first ferroelectric material, a first paraelectric material or a first anti-ferroelectric material on the first electrode layer and etching the first material layer stack;
depositing a first encapsulation layer on the first plurality of memory devices and on the first electrode layer;
etching the first electrode layer and the first encapsulation layer to form a first plate electrode extending beyond sidewalls of the first plurality of memory devices;
depositing a second encapsulation layer on the first encapsulation layer, on sidewalls of the first plate electrode and on the etch stop layer;
depositing a second dielectric on the second encapsulation layer;
forming a signal electrode on the first plate electrode by etching the second dielectric and the first encapsulation layer;
forming a first plurality of via electrodes, wherein individual ones of the first plurality of via electrodes are formed on individual ones of the first plurality of memory devices by a second process comprising:
forming a second opening in the second dielectric and in the first encapsulation layer and in the second encapsulation layer; and
depositing a second conductive hydrogen barrier layer and a second conductive material in the second opening;
forming a second electrode structure coupled with the signal electrode;
depositing a second electrode layer on the second electrode structure, wherein the second electrode layer is above the first plurality of via electrodes;
forming a second plurality of memory devices by depositing a second material layer stack comprising a second ferroelectric material, a second paraelectric material or a second anti-ferroelectric material on the second electrode layer and etching the second material layer stack;
depositing a third encapsulation layer on the second plurality of memory devices and on the second electrode layer;
etching the second electrode layer and the third encapsulation layer to form a second plate electrode extending beyond sidewalls of the second plurality of memory devices;
depositing a fourth encapsulation layer on the second encapsulation layer, on sidewalls of the second plate electrode; and
forming a second plurality of vias on individual ones of the second plurality of memory devices.
20. The method of claim 19 , wherein depositing the first encapsulation layer and the second encapsulation layer comprise depositing substantially conformally by a physical vapor deposition or an atomic layer deposition process, and further wherein depositing the first encapsulation layer and the second encapsulation layer comprising depositing to a thickness that is less than two times a spacing between adjacent memory devices of the first plurality of memory devices and of the second plurality of memory devices.