IP Library › Granted Patent US 12,324,359
Granted Patent B2
US 12,324,359 · App. 17/662,259 · Granted Jun 3, 2025

Method of manufacturing semiconductor structure and semiconductor structure

Inventor: Yulei Wu (Hefei, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
H10N50/80H10B61/00H10N50/01
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Quick Facts
Patent No.
US 12,324,359
App. No.
17/662,259
Granted
Jun 3, 2025
Kind
B2
Abstract

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a substrate; forming bottom contact structures in the substrate; forming a storage unit on each of the bottom contact structures; and forming shielding structures that each wrap around one of the storage units, wherein the shielding structures each include multiple dielectric layers and shielding layers arranged alternately.

Claims (53)

1. A method of manufacturing a semiconductor structure, the method comprising:

providing a substrate;

forming bottom contact structures in the substrate;

forming a storage unit on each of the bottom contact structures; and

forming shielding structures that each wrap around one of the storage units, wherein the shielding structures each comprise multiple dielectric layers and shielding layers arranged alternately;

wherein forming the bottom contact structures in the substrate comprising:

sequentially forming a third shielding material layer, a third dielectric material layer, a fourth shielding material layer, and a fourth dielectric material layer on the substrate;

forming a plurality of bottom contact holes in the substrate, the bottom contact holes each penetrating the third shielding material layer, the third dielectric material layer, the fourth shielding material layer, and the fourth dielectric material layer; and

filling a conductive material in each bottom contact hole.

2. The method of manufacturing the semiconductor structure according to claim 1 , the shielding structures each comprising:

a first dielectric layer, a first shielding layer, a second dielectric layer, and a second shielding layer that wrap around the storage unit in order.

3. The method of manufacturing the semiconductor structure according to claim 2 , wherein

the shielding structures have flush top surfaces, and the dimensions of the first dielectric layer, the first shielding layer, the second dielectric layer, and the second shielding layer increase in order in a height direction.

4. The method of manufacturing the semiconductor structure according to claim 1 , wherein each of the shielding structures also wrap part of each of the bottom contact structures.

5. The method of manufacturing the semiconductor structure according to claim 1 , wherein

a top of the storage unit is arc-shaped.

6. A method of manufacturing a semiconductor structure, the method comprising:

providing a substrate;

forming bottom contact structures in the substrate;

forming a storage unit on each of the bottom contact structures; and

forming shielding structures that each wrap around one of the storage units, wherein the shielding structures each comprise multiple dielectric layers and shielding layers arranged alternately;

wherein the shielding structures each comprising:

a first dielectric layer, a first shielding layer, a second dielectric layer, and a second shielding layer that wrap around the storage unit in order; and

wherein forming the bottom contact structures in the substrate comprising:

sequentially forming a third shielding material layer, a third dielectric material layer, a fourth shielding material layer, and a fourth dielectric material layer on the substrate;

forming a plurality of bottom contact holes in the substrate, the bottom contact holes each penetrating the third shielding material layer, the third dielectric material layer, the fourth shielding material layer, and the fourth dielectric material layer; and

filling a conductive material in each bottom contact hole.

7. The method of manufacturing the semiconductor structure according to claim 6 , wherein forming the storage unit on each of the bottom contact structures comprising:

sequentially forming a bottom electrode material layer, a free material layer, a tunneling barrier material layer, a fixed material layer, and a top electrode material layer on the fourth dielectric material layer;

forming a mask layer with opening patterns on the top electrode material layer; and

etching the bottom electrode material layer, the free material layer, the tunneling barrier material layer, the fixed material layer, and the top electrode material layer by using the mask layer, to form a plurality of discrete storage units on the fourth dielectric material layer, wherein the storage units are correspondingly connected to the bottom contact structures in a one-to-one manner.

8. The method of manufacturing the semiconductor structure according to claim 4 , wherein

forming the shielding structures that each wrap around one of the storage units comprising:

forming a fifth dielectric material layer on a surface of each storage unit;

partially removing the fourth dielectric material layer between the storage units;

forming a fifth shielding material layer on a surface of each fifth dielectric material layer;

partially removing the fourth shielding material layer between the storage units;

partially removing the third dielectric material layer between the storage units;

forming a sixth dielectric material layer on a surface of each fifth shielding material layer;

forming a sixth shielding material layer on a surface of each sixth dielectric material layer; and

partially removing the third shielding material layer between the storage units.

9. The method of manufacturing the semiconductor structure according to claim 8 , wherein

the partially removing the fourth dielectric material layer between the storage units, the fourth dielectric material layer under the fifth dielectric material layer on sidewalls of each storage unit is retained;

the partially removing the fourth shielding material layer between the storage units, the fourth shielding material layer under the fifth shielding material layer on the sidewalls of each storage unit is retained;

the partially removing the third dielectric material layer between the storage units, the third dielectric material layer under the fifth shielding material layer that is on the sidewalls of each storage unit is retained; and

the partially removing the third shielding material layer between the storage units, the third shielding material layer under the sixth shielding material layer that is on the sidewalls of each storage unit is retained.

10. The method of manufacturing the semiconductor structure according to claim 9 , wherein

the first dielectric layer comprises the fifth dielectric material layer and the fourth dielectric material layer that are connected as a whole;

the first shielding layer comprises the fifth shielding material layer and the fourth shielding material layer that are connected as a whole;

the second dielectric layer comprises the third dielectric material layer and the sixth dielectric material layer that are connected as a whole; and

the second shielding layer comprises the third shielding material layer and the sixth shielding material layer that are connected as a whole.

11. The method of manufacturing the semiconductor structure according to claim 10 , further comprising:

forming a top contact structure on each storage unit, the top contact structure penetrating the shielding layers and being connected to the top electrode material layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2022
From: WU, YULEI
To: CHANGXIN MEMORY TECHNOLOGIES, INC.
Reel/Frame 059838/0663 →
Priority Claims (1)
CN 202110340736.3 · Mar 30, 2021 · national
Continuity (2)
Continuation PCTCN2021112336 · Aug 12, 2021
Related Publication 20220320419A1 · Oct 6, 2022
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