Shortened single-level cell memory programming
A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.
1. A memory device comprising:
an array of memory cells configured as single-level cell memory; and
control logic operatively coupled to the array of memory cells, the control logic to perform operations comprising:
causing hardware initialization of a plurality of sub-blocks that are to be programmed within the array of memory cells;
causing a first sub-block of the plurality of sub-blocks to be preconditioned for a program operation;
causing a plurality of pages of data to be programmed to respective ones of the plurality of sub-blocks, comprising:
(i) causing a program pulse to be sent to the first sub-block to program a first page of the plurality of pages of data to the first sub-block;
(ii) causing a recovery operation to be performed at the first sub-block; and
(iii) causing a reduced seed operation to be performed at a second sub-block of the plurality of sub-blocks to precondition the second sub-block for programming; and
selectively causing a program verify to be performed on memory cells of the plurality of sub-blocks after programming the plurality of pages of data.
2. The memory device of claim 1 , wherein selectively causing the program verify to be performed comprises performing a single program verify on all of the plurality of sub-blocks together after each of the plurality of sub-blocks is in a programmed state.
3. The memory device of claim 1 , wherein the operations further comprise causing the plurality of pages of data to be loaded into a page buffer before performing the hardware initialization.
4. The memory device of claim 1 , wherein the reduced seed operation takes a period of time that is shorter than that for preconditioning the first sub-block.
5. The memory device of claim 1 , wherein causing the plurality of pages of data to be programmed further comprises:
(iv) causing a program pulse to be sent to the second sub-block to program a second page of the plurality of pages of data to the second sub-block;
(v) causing a recovery operation to be performed at the second sub-block; and
repeating (iii) through (v) to program a remainder of the plurality of pages of data to the plurality of sub-blocks.
6. The memory device of claim 1 , wherein the operations further comprise:
causing a check verification operation be performed at the plurality of sub-blocks to determine results of the program verify and that the pages of data have been completely programmed;
exiting a program operation of the plurality of sub-blocks in response to passing the check verification operation; and
causing a scan to be performed of the plurality of sub-blocks in response to failing the check verification operation.
7. A method comprising:
causing, by control logic of a memory device, hardware initialization of a plurality of sub-blocks that are to be programmed within an array of memory cells configured as single-level cell memory;
causing, by the control logic, a first sub-block of the plurality of sub-blocks to be preconditioned for a program operation;
causing, by the control logic, a plurality of pages of data to be programmed to respective ones of the plurality of sub-blocks, comprising:
(i) causing a program pulse to be sent to the first sub-block to program a first page of the plurality of pages of data to the first sub-block;
(ii) causing a recovery operation to be performed at the first sub-block; and
(iii) causing a reduced seed operation to be performed at a second sub-block of the plurality of sub-blocks to precondition the second sub-block for programming; and
selectively causing, by the control logic, a program verify to be performed on memory cells of the plurality of sub-blocks after programming the plurality of pages of data.
8. The method of claim 7 , wherein selectively causing the program verify to be performed comprises performing a single program verify on all of the plurality of sub-blocks together after each of the plurality of sub-blocks is in a programmed state.
9. The method of claim 7 , further comprising causing the plurality of pages of data to be loaded into a page buffer before performing the hardware initialization.
10. The method of claim 7 , wherein the reduced seed operation takes a period of time that is shorter than that for preconditioning the first sub-block.
11. The method of claim 7 , wherein causing the plurality of pages of data to be programmed further comprises:
(iv) causing a program pulse to be sent to the second sub-block to program a second page of the plurality of pages of data to the second sub-block;
(v) causing a recovery operation to be performed at the second sub-block; and
repeating (iii) through (v) to program a remainder of the plurality of pages of data to the plurality of sub-blocks.
12. The method of claim 7 , further comprising:
causing a check verification operation be performed at the plurality of sub-blocks to determine results of the program verify and that the pages of data have been completely programmed;
exiting a program operation of the plurality of sub-blocks in response to passing the check verification operation; and
causing a scan to be performed of the plurality of sub-blocks in response to failing the check verification operation.
13. An integrated circuit comprising:
at least one die comprising an array of memory cells configured as single-level cell memory; and
control logic operatively coupled to the at least one die, the control logic to perform operations comprising:
causing a plurality of pages of data to be loaded into a page buffer that is coupled with the array of memory cells;
causing hardware initialization of a plurality of sub-blocks that are to be programmed within the array of memory cells;
causing a first sub-block of the plurality of sub-blocks to be preconditioned for a program operation;
causing the plurality of pages of data to be programmed to respective ones of the plurality of sub-blocks, comprising:
(i) causing a program pulse to be sent to the first sub-block to program a first page of the plurality of pages of data to the first sub-block;
(ii) causing a recovery operation to be performed at the first sub-block; and
(iii) causing a reduced seed operation to be performed at a second sub-block of the plurality of sub-blocks to precondition the second sub-block for programming; and
selectively causing a program verify to be performed on memory cells of the plurality of sub-blocks after programming the plurality of pages of data.
14. The integrated circuit of claim 13 , wherein selectively causing the program verify to be performed comprises performing a single program verify on all of the plurality of sub-blocks together after each of the plurality of sub-blocks is in a programmed state.
15. The integrated circuit of claim 13 , wherein the reduced seed operation takes a period of time that is shorter than that for preconditioning the first sub-block.
16. The integrated circuit of claim 13 , wherein causing the plurality of pages of data to be programmed further comprises:
(iv) causing a program pulse to be sent to the second sub-block to program a second page of the plurality of pages of data to the second sub-block;
(v) causing a recovery operation to be performed at the second sub-block; and
repeating (iii) through (v) to program a remainder of the plurality of pages of data to the plurality of sub-blocks.
17. The integrated circuit of claim 13 , wherein the operations further comprise:
causing a check verification operation be performed at the plurality of sub-blocks to determine results of the program verify and that the pages of data have been completely programmed;
exiting a program operation of the plurality of sub-blocks in response to passing the check verification operation; and
causing a scan to be performed of the plurality of sub-blocks in response to failing the check verification operation.