Granted Patent B2

US 12,327,787 · App. 17/447,332 · Granted Jun 10, 2025

Inventors: Takashi Shimizu (Nagoya, JP); Takashi Fukushima (Yokkaichi, JP); Naomi Fukumaki (Yokkaichi, JP); Hiroko Tahara (Yokkaichi, JP); Kenichi Ide (Kuwana, JP)

Assignee: Kioxia Corporation

H01L23/5226H01L21/76802H01L21/76843H01L21/76877H01L23/53266H01L23/53271H10B41/27H10B43/27

Abstract

Claims (14)

1. A semiconductor memory device comprising:

a first stacked body including a plurality of first conductive layers and a plurality of insulating films alternatively stacked in a first direction, the plurality of first conductive layers each including tungsten;

a second stacked body provided adjacent to the first stacked body in a second direction and including a plurality of second conductive layers and the plurality of insulating films alternatively stacked in the first direction, the plurality of second conductive layers being respectively disposed in a same level in the first direction as a corresponding layer of the plurality of first conductive layers, the plurality of second conductive layers including a silicon containing an impurity, the second direction crossing the first direction;

a semiconductor layer extending in the first direction through an inside of the first stacked body;

a charge storage layer arranged between the plurality of first conductive layers and the semiconductor layer in the first stacked body;

a plurality of contact plugs respectively provided on a corresponding layer of the plurality of second conductive layers; and

the plurality of first conductive layers, which include the tungsten, are in direct contact on a same plane with the plurality of second conductive layers, which include the silicon containing the impurity, respectively.

2. The semiconductor memory device according to claim 1 , wherein pillar-shaped bodies that are each provided on the corresponding layer of the plurality of second conductive layers in such a manner as to be in contact with the corresponding layer and extend in the first direction are all the plurality of contact plugs.

3. The semiconductor memory device according to claim 1 , wherein the plurality of second conductive layers include polysilicon containing an impurity.

4. The semiconductor memory device according to claim 1 , further comprising a third stacked body provided adjacent to the first stacked body in a third direction and including a plurality of third conductive layers and the plurality of insulating films alternatively stacked in the first direction, the plurality of third conductive layers being respectively disposed in a same level in the first direction as a corresponding layer of the plurality of first conductive layers, the plurality of third conductive layers including silicon containing an impurity, the third direction crossing the first direction and the second direction.

5. The semiconductor memory device according to claim 4 , wherein a pillar-shaped body that is provided on a single third conductive layer of the plurality of third conductive layers in such a manner as to be in contact with the single third conductive layer is not provided on the third stacked body.

6. The semiconductor memory device according to claim 4 , wherein the plurality of third conductive layers include polysilicon containing an impurity.

7. The semiconductor memory device according to claim 1 , wherein no barrier metal is arranged between the plurality of first conductive layers and the plurality of insulating films and between the semiconductor layer and the plurality of insulating films.

8. The semiconductor memory device according to claim 7 , wherein the barrier metal includes titanium nitride.

Assignments (1)

Continuity (2)

References Cited (18)