Method and apparatus for suppressing cross current in inverter parallel system
A method and apparatus for suppressing cross current including: obtaining a common-mode current and a common-mode injection voltage of each inverter in an inverter parallel system; determining a virtual damping voltage of each inverter based on the common-mode current of each inverter and a preset common-mode damping factor, where if a direction in which a current flows out of the inverter is a positive direction, the preset common-mode damping factor is a negative value, or if a direction in which a current flows into the inverter is a positive direction, the preset common-mode damping factor is a positive value; superimposing the virtual damping voltage on the common-mode injection voltage of each inverter, to obtain a target common-mode voltage of each inverter; and controlling operation of each inverter based on the target common-mode voltage of each inverter and a differential mode voltage of each inverter.
1. A method for suppressing a cross current in an inverter parallel system, the method comprising:
obtaining a common-mode current and a common-mode injection voltage of each inverter in the inverter parallel system;
determining a virtual damping voltage of the each inverter based on the common-mode current and a preset common-mode damping factor of the each inverter, wherein if a direction in which a current flows out of the inverter is a positive direction, the preset common-mode damping factor is a negative value, or if a direction in which a current flows into the inverter is a positive direction, the preset common-mode damping factor is a positive value;
superimposing the virtual damping voltage on the common-mode injection voltage of the each inverter, to obtain a target common-mode voltage of the each inverter; and
controlling operation of the each inverter based on the target common-mode voltage of the each inverter and a differential mode voltage of the each inverter.
2. The method for suppressing a cross current in an inverter parallel system according to claim 1 , wherein the inverter parallel system comprises:
N inverter groups, wherein N is an integer greater than or equal to 2, the each inverter group comprises a first inverter and a second inverter, a direct current input terminal of the first inverter is connected to a first direct current power supply, a direct current input terminal of the second inverter is connected to a second direct current power supply, and
a negative electrode of the first direct current power supply is connected to a positive electrode of the second direct current power supply; and alternating current output terminals of N first inverters in the N inverter groups are connected to a first transformer, and alternating current output terminals of N second inverters in the N inverter groups are connected to a second transformer.
3. The method for suppressing a cross current in an inverter parallel system according to claim 2 , wherein negative electrodes of N first direct current power supplies in the N inverter groups are connected to each other.
4. The method for suppressing a cross current in an inverter parallel system according to claim 1 , wherein the inverter parallel system comprises:
N inverters, wherein N is an integer greater than or equal to 2, alternating current output terminals of the N inverters are connected to each other, and the alternating current output terminals of the N inverters are connected to a transformer; and direct current input terminals of the N inverters are respectively connected to N direct current power supplies, and positive electrodes of the N direct current power supplies are connected to each other.
5. The method for suppressing a cross current in an inverter parallel system according to claim 1 , wherein the inverter parallel system comprises:
N inverters, wherein N is an integer greater than or equal to 2, alternating current output terminals of the N inverters are connected to each other, and the alternating current output terminals of the N inverters are connected to a transformer; and direct current input terminals of the N inverters are respectively connected to N direct current power supplies, and negative electrodes of the N direct current power supplies are connected to each other.
6. The method for suppressing a cross current in an inverter parallel system according to claim 1 , wherein obtaining the common-mode injection voltage of the each inverter further comprises:
determining the common-mode injection voltage of the each inverter based on a common-mode voltage injection mode of the each inverter.
7. The method for suppressing a cross current in an inverter parallel system according to claim 6 , wherein the common-mode voltage injection mode comprises SPWM, SVPWM, or DPWM.
8. The method for suppressing a cross current in an inverter parallel system according to claim 1 , wherein the target common-mode voltage is obtained through the following formulas:
U cmv =U cmv0 +U vir , and
U vir =i cmv R vir , wherein
U cmv is the target common-mode voltage, U cmv0 is the common-mode injection voltage, U vir is the virtual damping voltage, R vir is the preset common-mode damping factor, and i cmv is the common-mode current.
9. The method for suppressing a cross current in an inverter parallel system according to claim 8 , wherein the common-mode current is obtained through the following formula:
i cmv =( i a +i b +i c )/3, wherein
i a , i b , and i c each are a three-phase output current of the inverter, and i cmv is the common-mode current.
10. The method for suppressing a cross current in an inverter parallel system according to claim 1 , wherein the controlling operation of the each inverter based on the target common-mode voltage of the each inverter and the differential mode voltage of the each inverter further comprises:
superimposing the target common-mode voltage of the each inverter on the differential mode voltage of the each inverter, to obtain a modulation voltage of the each inverter; and
controlling the operation of the each inverter by using the modulation voltage of the each inverter as a drive signal of a switching element of the each inverter.
11. An apparatus for suppressing a cross current in an inverter parallel system, the apparatus comprising:
a processor configured to:
obtain a common-mode current and a common-mode injection voltage of each inverter in the inverter parallel system;
determine a virtual damping voltage of the each inverter based on the common-mode current and a preset common-mode damping factor of the each inverter, wherein after a direction in which a current flows out of the inverter is a positive direction, the preset common-mode damping factor is a negative value, or
after a direction in which a current flows into the inverter is a positive direction, the preset common-mode damping factor is a positive value;
superimpose the virtual damping voltage on the common-mode injection voltage of the each inverter, to obtain a target common-mode voltage of the each inverter; and
control, by using a controller, operation of the each inverter based on the target common-mode voltage that is of the each inverter and that is obtained by the processor and a differential mode voltage of the each inverter.
12. The apparatus for suppressing a cross current in an inverter parallel system according to claim 11 , wherein the inverter parallel system comprises:
N inverter groups, wherein N is an integer greater than or equal to 2, the each inverter group comprises a first inverter and a second inverter, a direct current input terminal of the first inverter is connected to a first direct current power supply, a direct current input terminal of the second inverter is connected to a second direct current power supply, and a negative electrode of the first direct current power supply is connected to a positive electrode of the second direct current power supply; and
alternating current output terminals of N first inverters in the N inverter groups are connected to a first transformer, and alternating current output terminals of N second inverters in the N inverter groups are connected to a second transformer.
13. The apparatus for suppressing a cross current in an inverter parallel system according to claim 12 , wherein negative electrodes of N first direct current power supplies in the N inverter groups are connected to each other.
14. The apparatus for suppressing a cross current in an inverter parallel system according to claim 11 , wherein the inverter parallel system comprises:
N inverters, wherein N is an integer greater than or equal to 2, alternating current output terminals of the N inverters are connected to each other, and the alternating current output terminals of the N inverters are connected to a transformer; and direct current input terminals of the N inverters are respectively connected to N direct current power supplies, and positive electrodes of the N direct current power supplies are connected to each other.
15. The apparatus for suppressing a cross current in an inverter parallel system according to claim 11 , wherein the inverter parallel system comprises:
N inverters, wherein N is an integer greater than or equal to 2, alternating current output terminals of the N inverters are connected to each other, and the alternating current output terminals of the N inverters are connected to a transformer; and direct current input terminals of the N inverters are respectively connected to N direct current power supplies, and negative electrodes of the N direct current power supplies are connected to each other.
16. The apparatus for suppressing a cross current in an inverter parallel system according to claim 11 , wherein the processor is further configured to:
determine the common-mode injection voltage of the each inverter based on a common-mode voltage injection mode of the each inverter.
17. The apparatus for suppressing a cross current in an inverter parallel system according to claim 16 , wherein the common-mode voltage injection mode comprises sine pulse width modulation (SPWM), space vector pulse width modulation (SVPWM), or discontinuity pulse width modulation (DPWM).
18. The apparatus for suppressing a cross current in an inverter parallel system according to claim 11 , wherein the target common-mode voltage is obtained through the following formulas:
U cmv =U cmv0 +U vir , and
U vir =i cmv R vir , wherein
U cmv is the target common-mode voltage, U cmv0 is the common-mode injection voltage, U vir is the virtual damping voltage, R vir is the preset common-mode damping factor, and i cmv is the common-mode current.
19. The apparatus for suppressing a cross current in an inverter parallel system according to claim 11 , wherein
the processor is further configured to:
superimpose the target common-mode voltage of the each inverter on the differential mode voltage of the each inverter, to obtain a modulation voltage of the each inverter; and
use the modulation voltage that is of the each inverter and that is obtained by the processor as a drive signal of a switching element of the each inverter, to control the operation of the each inverter.
20. A power supply system, comprising an inverter parallel system and the apparatus for suppressing the cross current in the inverter parallel system according to claim 11 , and the apparatus for suppressing the current in the inverter parallel system is configured to suppress the cross current in the inverter parallel system.