Power amplifier
View Patent ↗An ultra-wideband power amplifier includes a preamplifier circuit and a post amplifier circuit. The preamplifier circuit includes a first DC blocking capacitor C 1 , a first decoupling capacitor C 2 , a second decoupling capacitor C 3 , a stabilizing resistor R in , a first AC blocking resistor RG 1 , a first input inductor L 1 , a second input inductor L 2 , an output inductor L 3 , a first input microstrip line MLIN 1 , a second input microstrip line MLIN 2 , an output microstrip line MLIN 3 , and a first transistor Q 1 . A first end of the first DC blocking capacitor C 1 acts as an input terminal of the preamplifier circuit, and a second end of the first DC blocking capacitor C 1 is connected to the stabilizing resistor R in , the first input inductor L 1 , the first input microstrip line MLIN 1 , and a gate electrode of the first transistor Q 1 sequentially. One end of the first decoupling capacitor C 2 is grounded.
1. A power amplifier, comprising:
1) a preamplifier circuit, the preamplifier circuit comprising a first DC blocking capacitor C 1 , a first decoupling capacitor C 2 , a second decoupling capacitor C 3 , a stabilizing resistor Rill, a first AC blocking resistor RG 1 , a first input inductor L 1 , a second input inductor L 2 , an output inductor L 3 , a first input microstrip line MLIN 1 , a second input microstrip line MLIN 2 , an output microstrip line MLIN 3 , and a first transistor Q 1 ; and
2) a post amplifier circuit, the post amplifier circuit comprising a first gate microstrip line MLIN 4 , a second gate microstrip line MLIN 5 , a third gate microstrip line MLIN 6 , a fourth gate microstrip line MLIN 7 , a drain inductor L 4 , a first drain microstrip line MLIN 8 , a second drain microstrip line MLIN 9 , a second AC blocking resistor RG 2 , a third decoupling capacitor C 5 , a fourth decoupling capacitor C 6 , a third DC blocking capacitor C 7 , an AC blocking inductor L 5 , a second transistor Q 2 , a third transistor Q 3 , and a fourth transistor Q 4 ;
wherein:
a first end of the first DC blocking capacitor C 1 acts as an input terminal of the preamplifier circuit, and a second end of the first DC blocking capacitor C 1 is connected to the stabilizing resistor R in , the first input inductor L 1 , the first input microstrip line MLIN 1 , and a gate electrode of the first transistor Q 1 sequentially;
a first end of the first decoupling capacitor C 2 is grounded, and a second end of the first decoupling capacitor C 2 is connected to the first AC blocking resistor RG 1 , the second input inductor L 2 , the second input microstrip line MLIN 2 , and the gate electrode of the first transistor Q 1 sequentially;
a junction of the first decoupling capacitor C 2 and the first AC blocking resistor RG 1 is connected to a gate supply voltage V gs1 ;
a first end of the second decoupling capacitor C 3 is grounded, and a second end of the second decoupling capacitor C 3 is connected to the output inductor L 3 , the output microstrip line MLIN 3 , and a drain electrode of the first transistor Q 1 ; a junction of the second decoupling capacitor C 3 and the output inductor L 3 is connected to a drain supply voltage V ds1 ; and a junction of the output inductor L 3 and the output microstrip line MLIN 3 acts as an output terminal of the preamplifier circuit;
a second DC blocking capacitor C 4 is disposed between the preamplifier circuit and the post amplifier circuit;
a first end of the first gate microstrip line MLIN 4 acts as an input terminal of the post amplifier circuit, and a second end of the first gate microstrip line MLIN 4 is connected to the second gate microstrip line MLIN 5 , the third gate microstrip line MLIN 6 , the fourth gate microstrip line MLIN 7 , the second AC blocking resistor RG 2 , and the third decoupling capacitor C 5 sequentially; and one end of the third decoupling capacitor C 5 is grounded;
a junction of the second AC blocking resistor RG 2 and the third decoupling capacitor C 5 is connected to a gate supply voltage V gs2 ; a junction of first gate microstrip line MLIN 4 and the second gate microstrip line MLIN 5 is connected to a gate electrode of the second transistor Q 2 ; a junction of the second gate microstrip line MLIN 5 and the third gate microstrip line MLIN 6 is connected to a gate electrode of the third transistor Q 3 ; a junction of the third gate microstrip line MLIN 6 and the fourth gate microstrip line MLIN 7 is connected to a gate electrode of the fourth transistor Q 4 ;
the drain inductor L 4 is disposed between drain electrodes of the second transistor Q 2 and the third transistor Q 3 ;
the first drain microstrip line MLIN 8 is disposed between drain electrodes of the third transistor Q 3 and the fourth transistor Q 4 ; and
a junction of the first drain microstrip line MLIN 8 and the fourth transistor Q 4 is connected to a first end of the second drain microstrip line MLIN 9 ; a second end of the second drain microstrip line MLIN 9 is connected to first ends of the fourth decoupling capacitor C 6 , the AC blocking inductor L 5 , and the third DC blocking capacitor C 7 ; a second end of the fourth decoupling capacitor C 6 is grounded; a second end of the AC blocking inductor L 5 is connected to a voltage source V ds2 ; and a second end of the third DC blocking capacitor C 7 acts as an output terminal of the post amplifier circuit.