System and method for calibrating an analog-to-digital converter using a rational sampling frequency calibration digital-to-analog converter

1. An analog-to-digital conversion system, comprising:

a clock generator configured to generate a first clock signal at a first frequency;

an analog-to-digital converter (ADC) configured to convert an input analog signal to a digital signal, wherein the ADC operates based on the first clock signal at the first frequency;

a calibration digital-to-analog converter (DAC) configured to generate an analog reference signal from digital reference data;

a fractional rate clock generator configured to generate a second clock signal from the first clock signal or from a third clock signal, wherein the second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency, wherein the third clock signal is at a third frequency having an integer frequency relation with the first frequency;

an equalizer configured to process an output of the ADC to remove a distortion incurred by the ADC; and

an adaptation circuitry configured to generate coefficients for the equalizer based on the output of the ADC to the analog reference signal.

2. The analog-to-digital conversion system of claim 1 , further comprising:

a data rate conversion block configured to supply the digital reference data received at the first frequency to the calibration DAC at the second frequency.

3. The analog-to-digital conversion system of claim 2 , wherein the data rate conversion block is configured to skip q-p samples out of q received samples, wherein the fractional rate is p/q.

4. The analog-to-digital conversion system of claim 2 , wherein the data rate conversion block is a digital fractional rate filter configured to convert the digital reference data from the first frequency to the second frequency.

5. The analog-to-digital conversion system of claim 1 , wherein the fractional rate is close to one.

6. The analog-to-digital conversion system of claim 1 , wherein the fractional rate clock generator comprises:

a first divider configured to divide the first clock signal by a factor of q;

a ring oscillator configured to generate the second clock signal;

a second divider configured to divide an output of the ring oscillator by a factor of p;

a phase detector configured to detect a phase difference between outputs of the first divider and the second divider and generate an error signal; and

a loop filter configured to filter the error signal to generate a control signal to the ring oscillator for controlling an oscillating frequency of the ring oscillator.

7. The analog-to-digital conversion system of claim 6 , wherein p and q are positive integers.

8. The analog-to-digital conversion system of claim 6 , wherein p and q are rational numbers.

9. The analog-to-digital conversion system of claim 1 , wherein the fractional rate clock generator comprises:

a divider configured to generate a reference clock signal by dividing the first clock signal by a factor of q;

a delay line comprising a chain of delay gates coupled in series, wherein the delay line receives the reference clock signal at one end and outputs a delayed reference clock signal at the other end;

a phase detector configured to detect a phase difference between the reference clock signal and the delayed reference clock signal to generate an error signal;

a loop filter configured to filter error signals;

a delay control block configured to generate a control signal based on the filtered error signals, wherein the delay line is controlled by the control signal; and

an edge combiner configured to combine p+1 clock phases tapped from the delay line to generate the second clock signal.

10. The analog-to-digital conversion system of claim 1 , wherein the fractional rate clock generator comprises:

a divider configured to generate a reference clock signal by dividing the first clock signal by a factor of q; and

a frequency multiplier configured to multiply the reference clock signal by a factor of p.

11. The analog-to-digital conversion system of claim 10 , wherein the frequency multiplier is an injection-locked ring oscillator.

12. The analog-to-digital conversion system of claim 1 , further comprising an LC filter configured to filter the analog reference signal from the calibration DAC.

13. A user equipment including the analog-to-digital conversion system of claim 1 .

14. A base station including the analog-to-digital conversion system of claim 1 .

15. A method for calibrating an analog-to-digital converter (ADC), comprising:

generating a first clock signal at a first frequency;

converting, by an ADC, an input analog signal to a digital signal, wherein the ADC operates based on the first clock signal at the first frequency;

generating, by a calibration digital-to-analog converter (DAC), an analog reference signal from digital reference data;

generating, by a fractional rate clock generator, a second clock signal from the first clock signal or from a third clock signal, wherein the second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency, wherein the third clock signal is at a third frequency having an integer frequency relation with the first frequency;

processing, by an equalizer, an output of the ADC to remove a distortion incurred by the ADC; and

generating coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.

16. The method of claim 15 , further comprising:

supplying the digital reference data received at the first frequency to the calibration DAC at the second frequency.

17. The method of claim 15 , wherein the fractional rate is close to one.

18. The method of claim 15 , further comprising:

filtering the analog reference signal from the calibration DAC.

19. A non-transitory machine-readable medium including code, when executed, to cause a machine to perform a method of claim 15 .