Circuit and method for charge device model protection
Embodiments included herein are directed towards a charge device model (“CDM”) protection circuit. The circuit may include a power supply, a power clamp operatively connected to the power supply, at least one diode connected with the power clamp, a field effect transistor (“FET”) operatively connected with the at least one diode and a trigger mechanism configured to activate the FET.
1. A charge device model (“CDM”) protection circuit comprising:
a power supply;
a primary power clamp operatively connected to the power supply;
at least one diode from a first set of diodes connected with the primary power clamp;
a second set of diodes operatively connected with the first set of diodes; and
a secondary power clamp operatively connected with at least one diode from the second set of diodes, wherein the secondary power clamp occupies less surface area than the primary power clamp, the secondary power clamp including:
a field effect transistor (“FET”) configured to vary an amplitude of an output voltage, wherein the FET includes a pulldown n-channel metal-oxide semiconductor (“nMOS”) and a pullup p-channel metal-oxide semiconductor (“pMOS”), wherein the at least one diode from the second set of diodes is connected to the secondary power clamp at a node disposed between the pulldown nMOS and the pullup pMOS, such that the at least one diode from the second set of diodes is in position to regulate a voltage level between the pulldown nMOS and the pullup pMOS,
a trigger mechanism configured to activate the FET, wherein the trigger mechanism includes a resistor/capacitor (“RC”) network, and
a triggering inverter configured to receive an input from the RC network, wherein the input of the triggering inverter is held to ground via a capacitor of the RC network.
2. A charge device model (“CDM”) protection method comprising:
providing a power supply, a primary power clamp operatively connected to the power supply, at least one diode from a first set of diodes connected with the primary power clamp, a second set of diodes operatively connected with the first set of diodes; a secondary power clamp operatively connected with at least one diode from the second set of diodes, wherein the secondary power clamp occupies less surface area than the primary power clamp, the secondary power clamp including a field effect transistor (“FET”) configured to vary an amplitude of an output voltage, a trigger mechanism configured to activate the FET, wherein the trigger mechanism includes a resistor/capacitor (“RC”) network, and a series impedance connected with at least one victim device, wherein the FET includes a pulldown n-channel metal-oxide semiconductor (“nMOS”) and a pullup p-channel metal-oxide semiconductor (“pMOS”), wherein the at least one diode from the second set of diodes is connected to the secondary power clamp at a node disposed between the pulldown nMOS and the pullup pMOS;
receiving a current at the at least one diode and the primary power clamp;
holding a triggering inverter input to ground via a capacitor of the RC network;
pulling up an output of the triggering inverter;
grounding the at least one diode; and
reducing a maximum voltage provided to the at least one victim device based upon, at least in part, the grounded at least one diode, wherein the secondary power clamp further includes a triggering inverter configured to receive an input from the RC network, wherein the input of the triggering inverter is held to ground via the capacitor of the RC network.
3. The CDM protection method of claim 2 , further comprising:
receiving an input from the RC network at an inverter.
4. The CDM protection method of claim 2 , wherein a gate of the inverter is held high using a resistor during normal operation.
5. The CDM protection method of claim 2 , wherein the inverter is powered via the power supply.
6. A charge device model (“CDM”) protection circuit comprising:
a power supply;
a primary power clamp operatively connected to the power supply;
a first set of diodes connected with the primary power clamp;
a second set of diodes connected with the first set of diodes;
a secondary power clamp operatively connected with the second set of diodes, wherein the secondary power clamp occupies less surface area than the primary power clamp, the secondary power clamp including:
a capacitor configured to receive and store a portion of excess charge after passing through at least one diode from the second set of diodes, and
a resistor operatively connected to the capacitor, wherein the resistor is configured to control the rate of discharge of the capacitor, wherein the at least one diode from the second set of diodes is connected to the secondary power clamp at a node disposed between the capacitor and the resistor.
7. The CDM protection circuit of claim 6 , wherein the CDM circuit has two modes of operation, a normal mode and an electrostatic discharge (ESD) mode.
8. The CDM protection circuit of claim 7 , wherein at least one diode from the second set of diodes is configured to have a reversed bias when operating in the normal mode.
9. The CDM protection circuit of claim 7 , wherein the power supply decreases towards ground and the capacitor discharges towards ground through the resistor when operating in the ESD mode.
10. The CDM protection circuit of claim 6 , wherein the resistor holds a voltage level inside the secondary power clamp to be equal to the power supply when operating in the normal mode.
11. The CDM protection circuit of claim 6 , wherein the first set of diodes and the second set of diodes are connected through a secondary impedance.
12. The CDM protection circuit of claim 6 , wherein the second set of diodes are operatively connected to a different power supply than the first set of diodes.