IP Library › Granted Patent US 12,331,424
Granted Patent B2
US 12,331,424 · App. 18/040,991 · Granted Jun 17, 2025

Method for depositing an epitaxial layer on a substrate wafer

Inventors: Thomas Stettner (Waging am See, DE); Martin Wengbauer (Winhoering, DE)
Assignee: SILTRONIC AG
C30B25/16C30B25/12C30B25/18C30B29/06
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Quick Facts
Patent No.
US 12,331,424
App. No.
18/040,991
Granted
Jun 17, 2025
Kind
B2
Abstract

An epitaxial layer is deposited on a substrate wafer by a method including measuring an edge geometry of the wafer, placing the wafer at a position in a pocket of a susceptor of a device for depositing the layer based on the edge geometry, heating the wafer, and passing a process gas over the wafer. Thickness characteristic values are assigned to edge portions based on the edge geometry. The position in the pocket is determined as function of an expected change in the thickness characteristic value to an eccentricity E, which is determined by prior testing of the device. The function is a result of the shape of the pocket which has a boundary having a circular circumference. The distance from the wafer to the boundary of the pocket is less at thicker edge portions and greater at thinner edge portion so the layer has thicknesses inverse to the wafer thicknesses.

Claims (34)

1. A method for depositing an epitaxial layer on a substrate wafer comprising:

measuring an edge geometry of the substrate wafer, the substrate wafer having a thicker edge section and a thinner edge section opposite the thicker edge section;

placing the substrate wafer at a position in a pocket of a susceptor of a device for depositing the epitaxial layer, the pocket being surrounded by a boundary and the position being based on the edge geometry, wherein the position in the pocket is such that a first distance from the thicker edge section to the boundary of the pocket is less than a second distance from the thinner edge section to the boundary of the pocket;

beating the substrate wafer in the pocket, and

passing process gas over the substrate wafer while in the pocket such that an epitaxial layer thickness is greater on the thinner edge section than on the thicker edge section.

2. The method of claim 1 , further comprising assigning thickness characteristic values to edge portions of the substrate wafer based on the edge geometry wherein the position is determined by a function of an expected change in the thickness characteristic value to an eccentricity.

3. The method of claim 1 , wherein the boundary has a circular circumference.

4. The method of claim 1 , wherein a robot places the rate wafer in the pocket.

5. The method of claim 1 , further comprising a camera system to position the substrate wafer in the pocket.

6. The method of claim 1 , wherein a single-crystal silicon epitaxial layer is deposited on the substrate wafer.

7. The method of claim 1 , wherein the epitaxial layer is deposited from a vapor phase.

8. A method depositing an epitaxial layer on a substrate v aft comprising:

machining a substrate wafer such that it does not have a uniform edge thickness

measuring an edge geometry of the substrate wafer, the substrate wafer having a thicker edge section and a thinner edge section opposite the thicker edge section;

placing the substrate wafer at a pocket of a susceptor of a device for depositing the epitaxial layer, the pocket being surrounded by a boundary and the position being based on the edge geometry;

heating the substrate wafer in the pocket; and

passing process r the substrate wafer while in the pocket such that an epitaxial layer thickness is greater on the thinner edge section than on the thicker edge section.

9. The method of claim 1 , wherein measuring includes defining a map that assigns an ESFOR value to each sector corresponding to a thickness profile of the substrate wafer along its circumference.

10. The method of claim 1 , wherein a thinner epitaxial layer is applied to the thicker edge section and a thicker epitaxial layer is applied to the thinner edge section.

11. The method of claim 1 , wherein epitaxial layer has a thickness of 1 to 20 μm.

12. The method of claim 1 , wherein the substrate wafer has a diameter of at least 200 mm.

13. The method of claim 1 , wherein a self-learning system is employed to position the substrate wafer.

14. A method for depositing an epitaxial layer on a substrate wafer comprising:

measuring an edge geometry of the substrate wafer, the substrate wafer having a thicker edge section and a thinner edge section opposite the thicker edge section;

assigning thickness characteristic values to edge portions of the substrate wafer based on the edge geometry

placing the substrate wafer at a position in a pocket of a susceptor of a device for depositing the epitaxial layer, the pocket being surrounded by a boundary and the position being based on the edge geometry, wherein the position is determined by a function of an expected change in the thickness characteristic value to an eccentricity;

heating the substrate wafer in the pocket; and

passing process gas over the substrate wafer while in the pocket such that an epitaxial layer thickness is greater on the thinner edge section than on the thicker edge section.

15. The method of claim 14 , wherein the function is determined by prior testing of the device.

16. The method of claim 14 , wherein the thicker edge section has a greater thickness characteristic value than the thinner edge section.

17. The method of claim 16 , wherein a distance between the boundary of the susceptor and each edge portion of the substrate wafer corresponds to the thickness characteristic values of the edge portion.

18. The method of claim 14 , wherein the thickness characteristic values include a ESFOR or a ZDD.

19. The method of claim 14 , wherein each edge portion is up to 50% of a circumference of the substrate wafer.

20. The method of claim 14 , within each edge portion is 7 to 42% of a circumference of the substrate wafer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2023
From: STETTNER, THOMAS; WENGBAUER, MARTIN
To: SILTRONIC AG
Reel/Frame 062681/0548 →
Priority Claims (1)
EP 20191322 · Aug 17, 2020 · regional
Continuity (1)
Related Publication 20230265581A1 · Aug 24, 2023
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