System and method for automatic fault detection in an electronic design
Embodiments include herein are directed towards a method for automatic detection during a timing analysis. Embodiments may include reading, using a processor, design and power intent information associated with an electronic design and automatically identifying a plurality of inter-power domain paths from the design and power intent information. Embodiments may further include automatically filtering the plurality of inter-power domain paths to identify one or more faulty inter-power domain paths using a graph-based approach and automatically generating a report depicting the one or more faulty inter-power domain paths.
1. A computer-implemented method for automatic fault detection during a timing analysis comprising:
reading, using a processor, design and power intent information associated with an electronic design;
automatically identifying a plurality of inter-power domain paths from the design and power intent information;
automatically filtering the plurality of inter-power domain paths to identify one or more faulty inter-power domain paths using a graph-based approach, wherein identifying the one or more faulty inter-power domain paths reduces a search space; and
automatically generating a report depicting the one or more faulty inter-power domain paths.
2. The computer-implemented method of claim 1 , further comprising:
receiving a user input identifying a fault type or fault region.
3. The computer-implemented method of claim 1 , wherein the graph based approach includes generating an inter-power domain graph.
4. The computer-implemented method of claim 1 , wherein the inter-power domain graph includes a direct acyclic graph representation of connectivity and adjacency information of all power domain crossings in the electronic design.
5. The computer-implemented method of claim 4 , wherein the report includes at least one of exact power domain transition information, instance/net transition information, data path information, clock path information, and capture path information.
6. The computer-implemented method of claim 1 , wherein identifying one or more faulty inter-power domain paths is common path pessimism removal aware.
7. The computer-implemented method claim 1 , wherein identifying one or more faulty inter-power domain paths includes mining path level power domain transition and transition instance/net information including begin point, end point, and clock information.
8. A non-transitory computer-readable storage medium having stored thereon instructions for automatic fault detection during a timing analysis that when executed by a machine result in the following operations:
reading, using a processor, design and power intent information associated with an electronic design;
identifying a plurality of inter-power domain paths from the design and power intent information;
filtering the plurality of inter-power domain paths to identify one or more faulty inter-power domain paths using a graph-based approach, wherein filtering includes identifying an exact location of a power domain crossing, wherein identifying the one or more faulty inter-power domain paths reduces a search space; and
generating a report depicting the one or more faulty inter-power domain paths.
9. The non-transitory computer-readable storage medium of claim 8 , further comprising:
receiving a user input identifying a fault type or fault region.
10. The non-transitory computer-readable storage medium of claim 8 , wherein the graph based approach includes generating an inter-power domain graph.
11. The non-transitory computer-readable storage medium of claim 8 , wherein the inter-power domain graph includes a direct acyclic graph representation of connectivity and adjacency information of all power domain crossings in the electronic design.
12. The non-transitory computer-readable storage medium of claim 11 , wherein the report includes exact power domain transition information and instance/net transition information.
13. The non-transitory computer-readable storage medium of claim 8 , wherein identifying one or more faulty inter-power domain paths is common path pessimism removal aware.
14. The non-transitory computer-readable storage medium of claim 8 , wherein identifying one or more faulty inter-power domain paths includes mining path level power domain transition and transition instance/net information including begin point, end point, and clock information.
15. A system for automatic fault detection during a timing analysis comprising:
a computing device having at least one processor configured to read design and power intent information associated with an electronic design, the at least one processor further configured to identify a plurality of inter-power domain paths from the design and power intent information and filter the plurality of inter-power domain paths to identify one or more faulty inter-power domain paths using a graph-based approach, the at least one processor further configured to generate a report depicting the one or more faulty inter-power domain paths, wherein identifying the one or more faulty inter-power domain paths reduces a search space.
16. The system of claim 15 , wherein the at least one processor is further configured to receive a user input identifying a fault type or fault region.
17. The system of claim 15 , wherein the graph based approach includes generating an inter-power domain graph.
18. The system of claim 15 , wherein the inter-power domain graph includes a direct acyclic graph representation of connectivity and adjacency information of all power domain crossings in the electronic design.
19. The system of claim 18 , wherein the report includes exact power domain transition information and instance/net transition information.
20. The system of claim 15 , wherein identifying one or more faulty inter-power domain paths is common path pessimism removal aware.