Circuit and method to measure simulation to silicon timing correlation
An integrated circuit includes a programmable delay path comprising a plurality of path delay tuners configured to receive a plurality of control signals and add to the programmable delay path an amount of cell delay and an amount of wire delay that are based on the plurality of control signals. The integrated circuit further includes a controller configured to provide the plurality of control signals to the programmable delay path, receive a signal from the programmable delay path, and compare the signal to a reference signal.
1. An integrated circuit, comprising:
a programmable delay path comprising a plurality of path delay tuners configured to:
receive a plurality of control signals;
select an amount of cell delay and an amount of wire delay based on the plurality of control signals; and
add the amount of cell delay and the amount of wire delay that are selected to the programmable delay path; and
a second programmable delay path comprising a second plurality of path delay tuners configured to:
receive a second plurality of control signals; and
add to the second programmable delay path an amount of cell delay and an amount of wire delay that are based on the second plurality of control signals:
a controller configured to:
provide the plurality of control signals to the programmable delay path, receive a signal from the programmable delay path, and compare the signal to a reference signal; and
provide the second plurality of control signals to the second programmable delay path, receive a second signal from the programmable delay path, and compare the second signal to a second reference signal;
wherein the programmable delay path comprises a third plurality of transistors and the second programmable delay path comprises a fourth plurality of transistors having different channel widths than the third plurality of transistors.
2. The integrated circuit of claim 1 , wherein the controller is configured to determine whether a delay of the programmable delay path exceeds a threshold delay based on comparing the signal to the reference signal.
3. The integrated circuit of claim 1 , wherein the plurality of path delay tuners comprises a first path delay tuner configured to:
receive a first control signal of the plurality of control signals;
select a first amount of cell delay and a first amount of wire delay to add to the programmable delay path when the first control signal has a first state; and
select a second amount of wire delay and a second amount of cell delay to the programmable delay path when the first control signal has a second state.
4. The integrated circuit of claim 3 , wherein:
the first path delay tuner comprises:
a first selectable sub-path comprising a first number of logic gates; and
a second selectable sub-path comprising a second number of logic gates that is different from the first number of logic gates; and
the first path delay tuner is configured to select the first selectable sub-path when the first control signal has the first state and select the second selectable sub-path when the first control signal has the second state.
5. The integrated circuit of claim 4 , wherein:
the first path delay tuner further comprises a third selectable sub-path having the first number of logic gates and a fourth selectable sub-path having the second number of logic gates, the first and second selectable sub-paths comprising a first plurality of transistors and the third and fourth selectable sub-paths comprising a second plurality of transistors, the second plurality of transistors having different control terminal voltage thresholds than the first plurality of transistors; and
the first path delay tuner is further configured to receive a second control signal of the plurality of control signals, select the first and second selectable sub-paths when the second control signal has a first state, and select the third and fourth selectable sub-paths when the second control signal has a second state.