Power supply control method
A memory chip includes at least two memory blocks. In a method for controlling power supply for the memory blocks of the memory chip, each memory block receives a command for switching to standby mode. The commands are issued, for example by a processor, separately for each memory block in order to be able to individually place the memory block in standby mode.
1. A circuit, comprising:
a first memory chip including a first memory block and a second memory block;
wherein each of the first and second memory blocks is operable in a standby mode and an active mode;
a second memory chip separate from the first memory chip and including a state register configured to store a first mode control command signal for specifying standby or active mode for operation of the first memory block and further configured to store a second mode control command signal for specifying standby or active mode for operation of the second memory block;
a first latch having an input configured to receive the first mode control command signal, a clock input configured to receive a clock signal, and an output coupled to a mode control input of the first memory block;
a second latch having an input configured to receive the second mode control command signal, a clock input configured to receive said clock signal, and an output coupled to a mode control input of the second memory block; and
a processing circuit configured to generate said first and second mode control command signals for loading into the first and second registers, respectively.
2. The circuit of claim 1 , wherein a first logic state of the first mode control command signal commands operation of the first memory block in standby mode and a second logic state of the first mode control command signal commands operation of the first memory block in active mode.
3. The circuit of claim 1 , wherein a first logic state of the second mode control command signal commands operation of the second memory block in standby mode and a second logic state of the second mode control command signal commands operation of the second memory block in active mode.
4. The circuit of claim 1 , wherein the processing circuit asynchronously generates said first and second mode control command signals, and wherein assertion of the clock signal synchronizes the first and second mode control command signals.
5. The circuit of claim 1 , further comprising:
a logic circuit configured to logically combine the output of the first latch with a reset signal to generate a control signal coupled to the mode control input of the first memory block;
wherein said reset signal is asserted in response to a circuit reset, and said asserted reset signal, when logically combined with the output of the first latch, commands operation of the first memory block in sleep mode.
6. The circuit of claim 1 , further comprising:
a logic circuit configured to logically combine the output of the second latch with a reset signal to generate a control signal coupled to the mode control input of the second memory block;
wherein said reset signal is asserted in response to a circuit reset, and said asserted reset signal, when logically combined with the output of the second latch, commands operation of the second memory block in sleep mode.
7. The circuit of claim 1 , further comprising:
a logic circuit configured to logically combine the output of the first latch with a reset signal to generate a control signal coupled to the mode control input of the first memory block;
wherein said reset signal is asserted in response to a circuit reset, and said asserted reset signal, when logically combined with the output of the first latch, commands operation of the first memory block in active mode.
8. The circuit of claim 1 , further comprising:
a logic circuit configured to logically combine the output of the second latch with a reset signal to generate a control signal coupled to the mode control input of the second memory block;
wherein said reset signal is asserted in response to a circuit reset, and said asserted reset signal, when logically combined with the output of the second latch, commands operation of the second memory block in active mode.
9. A circuit, comprising:
a memory chip including at least two memory blocks;
a non-volatile memory separate from the at least two memory blocks that is configured to store a mode command for each memory block, wherein said mode command indicates whether the memory block is to be in one of a standby mode and an active mode; and
a logic circuit that operates in response to an assertion of a reset signal to:
logic AND the mode command for each memory block from the non-volatile memory to each memory block with said reset signal in order to configure the memory block to be in the standby mode when the mode command has a first logic value and configure the memory block to be in the active mode when the mode command has a second logic value.
10. The circuit according to claim 9 , wherein the non-volatile memory comprises a register that is separate from the memory blocks.
11. The circuit according to claim 9 , wherein the memory chip includes exactly two memory blocks each corresponding to a different physical region inside the memory chip.
12. The circuit according to claim 9 , wherein each memory block of the memory chip is powered by a voltage equal to about 3.3 V.
13. The circuit according to claim 9 , wherein each memory block consumes, in standby mode, an electric current with an intensity equal to about 0.1 μA.
14. The circuit according to claim 13 , wherein each memory block consumes, in active mode, an electric current with an intensity about five hundred times greater than in standby mode.
15. The circuit according to claim 9 , wherein the memory chip is a flash memory chip.
16. The circuit according to claim 9 , wherein the reset signal is generated in response to reset of a processor.
17. The circuit according to claim 16 , wherein the memory chip and the processor are part of a microcontroller.