Memory system and method of controlling non-volatile memory
A memory system includes a non-volatile memory and a controller. The non-volatile memory includes at least one memory chip. The controller is electrically coupled to the non-volatile memory. The controller transmits a first instruction to the non-volatile memory, and transmits a second instruction to the non-volatile memory after transmitting the first instruction. The first instruction and the second instruction form a series of sequences. In a case where the non-volatile memory satisfies a condition, the second instruction is transmitted to the non-volatile memory after a first period following transmission of the first instruction elapses. In a case where the non-volatile memory does not satisfy the condition, the second instruction is transmitted to the non-volatile memory after a second period following transmission of the first instruction elapses. The second period is different from the first period.
1. A memory system comprising:
a non-volatile memory including at least one memory chip;
a controller electrically coupled to the non-volatile memory, and configured to:
transmit a first instruction to the non-volatile memory;
transmit a second instruction to the non-volatile memory after transmitting the first instruction;
determine whether the non-volatile memory includes an interface chip; and
in response to determining that the non-volatile memory includes the interface chip, the second instruction is transmitted to the non-volatile memory after a first period following transmission of the first instruction elapses,
in response to determining that the non-volatile memory does not include the interface chip, the second instruction is transmitted to the non-volatile memory after a second period following transmission of the first instruction elapses, and
the first period is different from the second period.
2. The memory system according to claim 1 , wherein
the first instruction and the second instruction form a series of sequences.
3. The memory system according to claim 1 , wherein
the controller is further configured to store data indicating whether the non-volatile memory includes the interface chip.
4. The memory system according to claim 3 , wherein
the controller is further configured to, before transmitting the first and second instructions to the non-volatile memory,
transmit a third instruction to the non-volatile memory, and
store data indicating whether the non-volatile memory includes the interface chip based on a response for the third instruction from the non-volatile memory.
5. The memory system according to claim 3 , wherein
the data indicating whether the non-volatile memory includes the interface chip is generated at the time of manufacture of the memory system.
6. The memory system according to claim 5 , wherein
the controller is further configured to determine whether to use the first period or the second period as a period between transmitting the first instruction and transmitting the second instruction based on a correspondence table in which the data indicating whether the non-volatile memory includes the interface chip and a physical address of the non-volatile memory are associated.
7. The memory system according to claim 1 , wherein
the controller and the non-volatile memory are electrically coupled by a first signal line,
the first instruction is one of assertion and negation of a first signal transmitted from the controller to the non-volatile memory via the first signal line, and
the second instruction is another one of assertion and negation of the first signal.
8. The memory system according to claim 1 , wherein
the controller and the non-volatile memory are electrically coupled by a first signal line and a second signal line,
the first instruction is assertion of a first signal transmitted from the controller to the non-volatile memory via the first signal line, and
the second instruction is assertion of a second signal transmitted from the controller to the non-volatile memory via the second signal line.
9. The memory system according to claim 1 , wherein the second period is shorter than the first period.
10. The memory system according to claim 1 , wherein
the controller is further configured to:
transmit, to the non-volatile memory, an instruction indicating a timing of taking in a command for requesting output of data from the non-volatile memory, as the first instruction, and
transmit, to the non-volatile memory, an instruction indicating a timing of output of the data from the non-volatile memory, as the second instruction.
11. The memory system according to claim 1 , wherein the controller includes at least one of a system-on-a-chip (SoC), a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).
12. The memory system according to claim 1 , wherein the non-volatile memory includes at least one of a NAND flash memory, a magnetoresistive random access memory (MRAM), a phase change random access memory (PCRAM), or a resistive random access memory (ReRAM).
13. A method of controlling a plurality of non-volatile memories each having at least one memory chip, the plurality of the non-volatile memories including at least a first non-volatile memory and a second non-volatile memory, the method comprising:
transmitting a first instruction to the first non-volatile memory and the second non-volatile memory; and
determining that the first non-volatile memory includes an interface chip;
in response to determining that the first non-volatile memory includes the interface chip, transmitting a second instruction to the first non-volatile memory after a first period following the first instruction elapses,
determining that the second non-volatile memory does not include the interface chip; and
in response to determining that the second non-volatile memory does not include the interface chip, transmitting the second instruction to the second non-volatile memory after a second period following the first instruction elapses, the second period being different from the first period.
14. The method according to claim 13 , wherein the first instruction and the second instruction form a series of sequences.
15. The method according to claim 13 , further comprising:
storing data indicating whether the plurality of the non-volatile memories each includes the interface chip.
16. The method according to claim 15 , wherein
the plurality of the non-volatile memories are each included in a memory system, and the data indicating whether the plurality of the non-volatile memories each includes the interface chip is generated at the time of manufacturing the memory system.
17. The method according to claim 16 , further comprising:
using either the first period or the second period based on a correspondence table in which the data indicating whether the plurality of the non-volatile memories each includes the interface chip and a physical address of the plurality of the non-volatile memories are associated.
18. The method according to claim 13 , further comprising:
before transmitting the first and second instructions to the first non-volatile memory and the second non-volatile memory,
transmitting a third instruction to the first non-volatile memory and the second non-volatile memory, and
storing data indicating whether the first non-volatile memory and the second non-volatile memory each includes the interface chip based on a response for the third instruction from the first non-volatile memory and the second non-volatile memory.
19. The method according to claim 13 , further comprising:
communicating with each of the plurality of the non-volatile memories by a first signal line, wherein
the first instruction is one of assertion and negation of a first signal transmitted to each of the plurality of the non-volatile memories via the first signal line, and
the second instruction is another one of assertion and negation of the first signal.
20. The method according to claim 13 , wherein the second period is shorter than the first period.