Semiconductor structure and method of forming thereof

1. A method of forming a semiconductor structure, comprising:

forming a plurality of conductors in a first dielectric layer on a substrate, wherein the conductors extend in a first direction;

forming a plurality of first conductive vias in a second dielectric layer on the substrate, wherein each of the first conductive vias overlaps one of the conductors;

forming a third dielectric layer on the substrate;

forming a plurality of electrodes in the third dielectric layer, wherein each of the electrodes overlaps one of the first conductive vias;

forming a hard mask on the third dielectric layer;

forming a plurality of mandrel exposures on the hard mask, wherein the mandrel exposures extend in a second direction different from the first direction;

forming a plurality of patterning spacers on sidewalls of the mandrel exposures;

removing the mandrel exposures;

patterning the hard mask based on the patterning spacers; and

forming a plurality of conductive lines in the third dielectric layer based on the patterned hard mask, wherein the conductive lines extend in the second direction and are separated from the electrodes in the second direction, and each of the conductive lines overlaps a corresponding one of the first conductive vias.

2. The method of claim 1 , wherein the third dielectric layer is directly above or directly below the second dielectric layer.

3. The method of claim 1 , wherein forming the patterning spacers on the sidewalls of the mandrel exposures comprises:

depositing a spacer layer covering the mandrel exposures and a top surface of the third dielectric layer; and

etching the spacer layer to expose tops of the mandrel exposures, wherein the spacer layer remaining on the sidewalls of the mandrel exposures forms the patterning spacers.

4. The method of claim 1 , wherein the mandrel exposures are formed to be aligned with the first conductive vias.

5. The method of claim 1 , wherein the conductors comprise a first conductor and a second conductor arranged in the first direction.

6. The method of claim 1 , wherein the conductors comprise a first conductor and a second conductor separated from each other in the second direction.

7. The method of claim 1 , wherein the electrodes comprises a first electrode and a second electrode arranged in the first direction.

8. The method of claim 7 , wherein the conductors comprise a first conductor, a second conductor and a third conductor, the second conductor is between the first conductor and the third conductor in the first direction, the second conductor is at a first side of the conductive lines, the first conductor and the third conductor is at an opposite second side of the conductive lines, and the first electrode and the second electrode overlap the first conductor and the third conductor, respectively.

9. The method of claim 1 , further comprising:

forming a second conductive via extending from one of the conductive lines to one of the conductors, wherein one of the electrodes overlaps the second conductive via.

10. A method of forming a semiconductor structure, comprising:

forming a first conductor in a first dielectric layer on a substrate, wherein the first conductor extends in a first direction;

forming a second dielectric layer on the first dielectric layer and a plurality of first conductive vias in the second dielectric layer, wherein the first conductive vias overlap the first conductor and are arranged in the first direction;

forming a third dielectric layer on the second dielectric layer;

forming a hard mask on the third dielectric layer;

forming a plurality of mandrel exposures on the hard mask, wherein the mandrel exposures are separated from each other in the first direction, extend in a second direction different from the first direction and respectively overlap the first conductive vias;

depositing a spacer layer on the mandrel exposures;

etching the spacer layer to form a plurality of patterning spacers on sidewalls of the mandrel exposures, wherein the patterning spacers extend in the second direction and are separated from each other in the first direction, each of the patterning spacers extends from a top of one of the mandrel exposures to a top surface of the hard mask, and immediately-adjacent two of the patterning spacers are located between immediately-adjacent two of the mandrel exposures;

removing the mandrel exposures;

patterning the hard mask by the patterning spacers; and

forming a plurality of first conductive lines and a plurality of second conductive lines in the third dielectric layer based on the patterned hard mask, wherein the first conductive lines and the second conductive lines extend in the second direction and alternatively arranged in the first direction, and each of the first conductive lines overlaps one of the first conductive vias.

11. The method of claim 10 , further comprising:

forming a second conductive via in the second dielectric layer, wherein the second conductive via is separated from the first conductive vias in the second direction and overlaps the first conductor; and

forming an electrode in the third dielectric layer, wherein the electrode overlaps the first conductor and is connected to second conductive via.

12. The method of claim 10 , further comprising:

forming a second conductor in the first dielectric layer, wherein the second conductor extends in the first direction and is separated from the first conductor in the second direction; and

forming a plurality of second conductive vias in the second dielectric layer, wherein the second conductive vias overlap the second conductor and are arranged in the first direction, and the second conductive lines are connected to the second conductive vias after the first conductive lines and the second conductive lines are formed.

13. The method of claim 12 , further comprising:

forming a third conductive via being in the second dielectric layer and overlaps the first conductor, wherein the third conductive via is separated from the first conductive vias in the second direction;

forming a fourth conductive via being in the second dielectric layer and overlaps the second conductor, wherein the fourth conductive via is separated from the second conductive vias in the second direction;

forming a first electrode being in the third dielectric layer and overlapping the third conductive via; and

forming a second electrode being in the third dielectric layer and overlapping the fourth conductive via.

14. The method of claim 10 , wherein a width of each of the first conductive lines in the first direction is equal to a width of each of the mandrel exposures in the first direction, and a width of each of the second conductive lines in the first direction is equal to a distance between immediately-adjacent two of the patterning spacers located between immediately-adjacent two of the mandrel exposures in the first direction.

15. The method of claim 10 , further comprising:

connecting the first conductive lines and the second conductive lines to a plurality of transistors on the substrate.

16. A semiconductor structure, comprising:

a substrate;

a first dielectric layer located at a first level on the substrate;

a plurality of conductors located in the first dielectric layer, wherein the conductors extend in a first direction;

a second dielectric layer located at a second level on the substrate;

a plurality of conductive vias located in the second dielectric layer, wherein each of the conductive vias overlaps one of the conductors;

a third dielectric layer located at a third level on the substrate;

a plurality of conductive lines located in the third dielectric layer, wherein the conductive lines extend in a second direction different from the first direction, a distance between immediately-adjacent two of the conductive lines is less than a distance between immediately-adjacent two of the conductive vias in the first direction, and each of the conductive lines overlaps one of the conductive vias; and

a plurality of electrodes located in the third dielectric layer, wherein each of the electrodes is connected to one of the conductive vias.

17. The semiconductor structure of claim 16 , wherein the first level is directly above or directly below the second level.

18. The semiconductor structure of claim 16 , wherein:

the conductors comprise a first conductor and a second conductor, the first conductor and the second conductor are located at a first side and a second side opposite to the first side of the conductive lines,

the conductive lines comprise a plurality of first conductive lines and a plurality of second conductive lines, the first conductive lines and the second conductive lines are alternatively arranged in the first direction and spatially isolated from each other, the first conductive lines are connected to the first conductor, and the second conductive lines are connected to the second conductor.

19. The semiconductor structure of claim 18 , wherein the conductive vias comprise a plurality of first conductive vias at the first side of the conductive lines and a plurality of second conductive vias at the second side of the conductive lines.

20. The semiconductor structure of claim 16 , further comprising:

a transistor located in the substrate and connected to the conductive lines.