Dielectric caps for power and signal line routing
A semiconductor interconnect structure comprises a substrate, a plurality of metal lines disposed relative to the substrate and a plurality of first and second caps disposed on the metal lines wherein the first caps comprise a first dielectric material and the second caps comprise a second dielectric material different from the first dielectric material.
1. A semiconductor interconnect structure, comprising:
a plurality of first metal lines and a plurality of second metal lines disposed vertically adjacent each other relative to a substrate; and
a plurality of first and second caps disposed on the respective plurality of first metal lines and the plurality of second metal lines, the first caps comprising a first dielectric material and the second caps comprising a second dielectric material different from the first dielectric material.
2. The semiconductor interconnect structure according to claim 1 , wherein the first and second caps are disposed in alternating relation on the respective plurality of first metal lines and the plurality of second metal lines.
3. The semiconductor interconnect structure according to claim 2 , wherein the plurality of first metal lines comprises a first metal material and wherein the plurality of second metal lines comprises a second metal material different from the first metal material.
4. The semiconductor interconnect structure according to claim 3 , wherein the plurality of first metal lines and the plurality of second metal lines are disposed in alternating relation.
5. The semiconductor interconnect structure according to claim 4 , wherein the first caps are disposed on at least some of the plurality of first metal lines and the second caps are disposed on at least some of the plurality of second metal lines.
6. The semiconductor interconnect structure according to claim 5 , wherein the plurality of first metal lines and the plurality of second metal lines are grouped to form a source region, a ground region and a signal region disposed between the source region and the ground region, each of the source region, the ground region and the signal region comprising the plurality of first metal lines and the plurality of second metal lines.
7. The semiconductor interconnect structure according to claim 6 , further comprising a first via coupled in parallel to adjacent first metal lines of the plurality of first metal lines in the source region and a second via coupled in parallel to adjacent second metal lines of the plurality of second metal lines in the ground region.
8. A semiconductor interconnect structure, comprising:
at least a pair of power regions located with respect to cell boundaries of a substrate, each of the power regions comprising first power lines and second power lines arranged in alternating relation and vertically adjacent each other, the first power lines comprising a first material and the second power lines comprising a second material different from the first material;
a signal region disposed vertically adjacent to the pair of power regions relative to the substrate, comprising a plurality of signal lines at least partially disposed between the pair of power regions, the signal lines comprising first and second signal lines arranged in alternating relation, the first signal lines comprising the first material and the second signal lines comprising the second material;
first caps disposed on at least one first power line of one power region of the pair of power regions and on at least one first signal line of the signal region, the first caps comprising a first dielectric material; and
second caps disposed on at least one second power line of another power region of the pair of power regions and on at least one second signal line of the signal region, the second caps comprising a second dielectric material different from the first dielectric material.
9. The semiconductor interconnect structure according to claim 8 , further comprising a first via coupling adjacent first power lines in parallel in the one power region of the pair of power regions with the adjacent first power lines being separated by a second power line of the second power lines having a second cap of the second caps disposed thereon.
10. The semiconductor interconnect structure according to claim 9 , wherein the one power region is arranged to provide a source voltage potential.
11. The semiconductor interconnect structure according to claim 10 , further comprising a second via coupling adjacent second power lines in parallel in the other power region of the pair of power regions with the adjacent second power lines being separated by a first power line of the first power lines having a first cap of the first caps disposed thereon.
12. The semiconductor interconnect structure according to claim 11 , wherein the other power region is arranged to provide a ground voltage potential.
13. The semiconductor interconnect structure according to claim 12 , further comprising at least a third via in communication with select ones of the first and second signal lines.
14. The semiconductor interconnect structure according to claim 13 , wherein each of the first, second, and third vias define an upper via portion having a width greater than a lower via portion.
15. The semiconductor interconnect structure according to claim 8 , wherein at least one of the first power lines and the second power lines is a discontinuous power line, and further including a signal line disposed in alignment with the discontinuous power line.
16. A semiconductor interconnect structure, comprising:
a plurality of first and second lines arranged in alternating relation and disposed vertically adjacent to each other relative to a substrate, the first lines comprising a first metal material and the second lines comprising a second metal material different from the first metal material;
first and second cap segments respectively disposed on select ones of the first and second lines, the first cap segments each comprising a first dielectric material and the second cap segments each comprising a second dielectric material different from the first dielectric material;
a first via in electrical parallel communication with adjacent first lines; and
a second via in electrical parallel communication with adjacent second lines;
wherein:
the adjacent first lines coupled by the first via are arranged to provide a source voltage potential;
the adjacent second lines coupled by the second via are arranged to provide a ground voltage potential; and
the first and second lines disposed between the adjacent first lines and the adjacent second lines are signal lines.
17. The semiconductor interconnect structure according to claim 16 , further comprising at least a third via in electrical connection with select ones of the signal lines.
18. The semiconductor interconnect structure according to claim 17 , wherein each of the first, second, and third vias define an upper via portion having a width greater than a lower via portion.
19. The semiconductor interconnect structure according to claim 16 , wherein the first metal material comprises one of ruthenium and copper and the second metal material comprises the other of ruthenium and copper.
20. The semiconductor interconnect structure according to claim 16 , wherein the first dielectric material comprises one of an oxide dielectric material and a nitride dielectric material and the second dielectric material comprises the other of the oxide dielectric material and the nitride dielectric material.