IP Library › Granted Patent US 12,336,209
Granted Patent B2
US 12,336,209 · App. 18/118,154 · Granted Jun 17, 2025

Semiconductor device and method for fabricating the same

Inventors: Chung-Fu Chang (Tainan, TW); Kuan-Hung Chen (Taichung, TW); Guang-Yu Lo (New Taipei, TW); Chun-Chia Chen (Tainan, TW); Chun-Tsen Lu (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10D30/024H01L21/0214H01L21/02164H01L21/022H01L21/28202H10D30/608H10D30/62H10D64/681
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Quick Facts
Patent No.
US 12,336,209
App. No.
18/118,154
Granted
Jun 17, 2025
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a gate dielectric layer on the fin-shaped structure; forming a gate electrode on the fin-shaped structure; performing a nitridation process to implant ions into the gate dielectric layer adjacent to two sides of the gate electrode; and forming an epitaxial layer adjacent to two sides of the gate electrode.

Claims (14)

1. A method for fabricating semiconductor device, comprising:

forming a fin-shaped structure on a substrate;

forming a gate dielectric layer on the fin-shaped structure, wherein the fin-shaped structure and the gate dielectric layer extend along a same direction in a top view;

forming a gate electrode on the fin-shaped structure;

performing a nitridation process to implant nitrogen ions into the gate dielectric layer adjacent to two sides of the gate electrode for dividing the gate dielectric layer into a first portion directly under the gate electrode and a second portion at two sides of the gate electrode;

forming a spacer on sidewalls of the gate electrode after performing the nitridation process;

forming lightly doped drain regions at the two sides of the gate electrode after performing the nitridation process;

removing a part of the second portion and a part of the fin-shaped structure to form recesses at the two sides of the gate electrode; and

forming an epitaxial layer in the recesses at the two sides of the gate electrode.

2. The method of claim 1 , wherein the first portion and the second portion comprise different materials.

3. The method of claim 2 , wherein the first portion comprises silicon oxide and the second portion comprises silicon oxynitride (SiON).

4. The method of claim 1 , wherein the fin-shaped structure and the gate dielectric layer are extended along a first direction on the substrate and the gate electrode is extended along a second direction.

5. The method of claim 4 , wherein the first direction is orthogonal to the second direction.

6. The method of claim 1 , wherein the nitridation process comprises a remote thermal nitridation process (RTN) or a decoupled plasma nitridation (DPN) process.

Priority Claims (1)
TW 108102399 · Jan 22, 2019 · national
Continuity (2)
Division 16282323 · Feb 22, 2019
Related Publication 20230207669A1 · Jun 29, 2023
References Cited (7)
US 6900092B2 · Ajmera et al. · 2005 [cited by applicant]
US 11631753B2 · Chang · 2023 [cited by applicant]
US 20150102386A1 · Chen · 2015 [cited by examiner]
US 20190164966A1 · Wang · 2019 [cited by examiner]
TW 201731106A · 2017 [cited by applicant]
TW 201820623A · 2018 [cited by applicant]
TW 201824555A · 2018 [cited by applicant]