IP Library › Granted Patent US 12,339,493
Granted Patent B2
US 12,339,493 · App. 17/605,500 · Granted Jun 24, 2025

Photonic chip and method of manufacture

Inventors: David Thomson (Southampton, GB); Graham Reed (Southampton, GB); Wei Wei Zhang (Southampton, GB); Martin Ebert (Southampton, GB)
Assignee: University of Southampton
G02B6/1228G02B6/131G02B6/132G02B6/136G02B2006/12176
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,339,493
App. No.
17/605,500
Granted
Jun 24, 2025
Kind
B2
Abstract

The invention provides a photonic chip comprising: a silicon substrate, an low refractive index layer above the silicon substrate, and a tapered waveguide above the low refractive index layer, the tapered waveguide having a first height at a first end of the tapered waveguide and a second height at a second end of the tapered waveguide, the second height being greater than the first height, and the tapered waveguide having a bottom surface that is closer to the substrate at the second end than at the first end. The invention further provides a method of manufacturing a photonic chip, the method comprising: providing a wafer comprising a silicon substrate, and an low refractive index layer above the silicon substrate, etching the low refractive index layer to form a tapered trench having a first height at a first end of the tapered trench and a second height at a second end of the tapered trench, the first second height being greater than the second first height, and the tapered trench having a bottom surface that is closer to the substrate at the first second end than at the second first end, and forming a tapered waveguide in the tapered trench.

Claims (36)

1. A photonic chip comprising:

a silicon substrate,

a first low refractive index layer above the silicon substrate,

an intermediate device layer above the first low refractive index layer,

a second low refractive index layer above the intermediate device layer,

a top device layer above the second low refractive index layer, and

a tapered waveguide above the second low refractive index layer, the tapered waveguide having a first height at a first end of the tapered waveguide and a second height at a second end of the tapered waveguide, the second height being greater than the first height, and

the tapered waveguide having a bottom surface that is closer to the substrate at the second end than at the first end.

2. The photonic chip of claim 1 , wherein the tapered waveguide is formed of silicon.

3. The photonic chip of claim 1 wherein a width of the tapered waveguide at the second end is greater than a width of the tapered waveguide at the first end.

4. The photonic chip of claim 1 , further comprising a first waveguide optically coupled to the first end of the tapered waveguide, the first waveguide having a third height.

5. The photonic chip of claim 4 , wherein a top surface of the tapered waveguide is coplanar with a top surface of the first waveguide.

6. The photonic chip of claim 4 , further comprising a second waveguide optically coupled to the second end of the tapered waveguide, the second waveguide having a fourth height, the fourth height being greater than the third height.

7. The photonic chip of claim 6 , wherein a top surface of the tapered waveguide is coplanar with a top surface of the second waveguide.

8. The photonic chip of claim 6 , wherein a width of the second waveguide is greater than a width of the first waveguide.

9. The photonic chip of claim 1 , wherein the tapered waveguide is contiguous with the top device layer at the first end of the tapered waveguide and is contiguous with the intermediate device layer at the second end.

10. The photonic chip of claim 1 , wherein the tapered waveguide is epitaxially grown.

11. The photonic chip of claim 1 , wherein the tapered waveguide is formed of polycrystalline silicon, amorphous silicon or single crystal silicon.

12. A method of manufacturing a photonic chip, the method comprising:

providing a double silicon-on-insulator wafer comprising a silicon substrate, a first low refractive index layer above the silicon substrate, an intermediate device layer above the first low refractive index layer, a second low refractive index layer above the intermediate device layer, and a top device layer above the second low refractive index layer,

etching the second low refractive index layer to form a tapered trench having a first height at a first end of the tapered trench and a second height at a second end of the tapered trench, the second height being greater than the first height, and

the tapered trench having a bottom surface that is closer to the substrate at the second end than at the first end, and

forming a tapered waveguide in the tapered trench.

13. The method of claim 12 , wherein the tapered waveguide is formed of silicon.

14. The method of claim 12 , wherein a width of the tapered trench at the second end is greater than a width of the tapered trench at the first end.

15. The method of claim 12 , wherein the trench is etched using reactive ion etching.

16. The method of claim 12 , wherein the photonic chip further comprises a first waveguide having a third height, wherein the first end of the tapered waveguide is optically coupled to the first waveguide.

17. The method of claim 16 , wherein a top surface of the tapered waveguide is coplanar with a top surface of the first waveguide.

18. The method of claim 16 , wherein the photonic chip further comprises a second waveguide having a fourth height, the fourth height being greater than the third height, and wherein the second end of the tapered waveguide is optically coupled to the second waveguide.

19. The method of claim 18 , wherein a top surface of the tapered waveguide is coplanar with a top surface of the second waveguide.

20. The method of claim 18 , wherein a width of the first waveguide is greater than a width of the second waveguide.

21. The method of claim 12 , wherein the step of forming the tapered waveguide comprises filling the tapered trench with polycrystalline silicon, amorphous silicon or single crystal silicon.

22. The method of claim 12 , wherein the step of forming the tapered waveguide comprises epitaxially growing silicon in the tapered trench.

23. The method of claim 12 , wherein the step of forming the tapered waveguide comprises etching the silicon in the trench to form a rib waveguide.

24. The method of claim 12 , wherein the wafer is a silicon-on-insulator wafer comprising the silicon substrate, the low refractive index layer and a silicon device layer.

25. The method of claim 12 , wherein the tapered waveguide is contiguous with the intermediate device layer at the second end of the tapered waveguide and is contiguous with the top device layer at the first end.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2022
From: THOMSON, DAVID; REED, GRAHAM; ZHANG, WEI WEI; EBERT, MARTIN
To: UNIVERSITY OF SOUTHAMPTON
Reel/Frame 058755/0001 →
Priority Claims (1)
GB 1905698 · Apr 24, 2019 · national
Continuity (1)
Related Publication 20220214498A1 · Jul 7, 2022
References Cited (87)
US 6058233A · Dragone · 2000 [cited by examiner]
US 6293688B1 · Deacon · 2001 [cited by examiner]
US 6768855B1 · Bakke · 2004 [cited by examiner]
US 6884327B2 · Pan · 2005 [cited by examiner]
US 6980720B2 · Gothoskar · 2005 [cited by examiner]
US 7005247B1 · Fong · 2006 [cited by examiner]
US 8045832B2 · Pan · 2011 [cited by examiner]
US 8170383B2 · Tokushima · 2012 [cited by examiner]
US 8472766B2 · Spector · 2013 [cited by examiner]
US 8483528B2 · Socci · 2013 [cited by examiner]
US 9076902B2 · Lui · 2015 [cited by applicant]
US 9323079B1 · Feng · 2016 [cited by examiner]
US 9366816B2 · Demaray · 2016 [cited by examiner]
US 9563014B2 · Pan · 2017 [cited by examiner]
US 9759864B2 · Painchaud · 2017 [cited by examiner]
US 9798082B2 · Demaray · 2017 [cited by examiner]
US 9958607B2 · Yanagisawa · 2018 [cited by examiner]
US 9989701B2 · Demaray · 2018 [cited by examiner]
US 10120130B2 · Demaray · 2018 [cited by examiner]
US 10197734B2 · Painchaud · 2019 [cited by examiner]
US 10514509B2 · Popovic · 2019 [cited by examiner]
US 20020191916A1 · Frish · 2002 [cited by examiner]
US 20030108319A1 · Chong · 2003 [cited by examiner]
US 20030118310A1 · Steinberg · 2003 [cited by examiner]
US 20030173208A1 · Pan · 2003 [cited by examiner]
US 20050105853A1 · Liu · 2005 [cited by examiner]
US 20050175287A1 · Pan · 2005 [cited by examiner]
US 20050183946A1 · Pan · 2005 [cited by examiner]
US 20100067846A1 · Tokushima · 2010 [cited by examiner]
US 20110026880A1 · Galli · 2011 [cited by examiner]
US 20110156183A1 · Liu · 2011 [cited by examiner]
US 20110170825A1 · Spector · 2011 [cited by examiner]
US 20140140659A1 · Demaray · 2014 [cited by examiner]
US 20140193115A1 · Popovic · 2014 [cited by examiner]
US 20150086153A1 · Ono et al. · 2015 [cited by applicant]
US 20150285997A1 · Pan · 2015 [cited by examiner]
US 20160266312A1 · Demaray · 2016 [cited by examiner]
US 20170017034A1 · Painchaud · 2017 [cited by examiner]
US 20170160468A1 · Yanagisawa · 2017 [cited by examiner]
US 20170371102A1 · Painchaud · 2017 [cited by examiner]
US 20180045886A1 · Demaray · 2018 [cited by examiner]
US 20180172909A1 · Asghari · 2018 [cited by examiner]
US 20180275341A1 · Demaray · 2018 [cited by examiner]
US 20180364416A1 · Li · 2018 [cited by examiner]
WO WO2011019887A2 · 2011 [cited by applicant]
H. Yanagawa, T. Shimizu, S. Nakamura and I. Ohyama, “Index-and-dimensional taper and its application to photonic devices,” in Journal of Lightwave Technology, vol. 10, No. 5, pp. 587-592, May 1992, doi: 10.1109/50.13609… [cited by examiner]
Junqiu Liu, Arslan S. Raja, Martin H. P. Pfeiffer, Clemens Herkommer, Hairun Guo, Michael Zervas, Michael Geiselmann, and Tobias J. Kippenberg, “Double inverse nanotapers for efficient light coupling to integrated photo… [cited by examiner]
Hyundai Park, Sanggi Kim, Jaegyu Park, Jiho Joo, and Gyungock Kim, “A fiber-to-chip coupler based on Si/SiON cascaded tapers for Si photonic chips,” Opt. Express 21, 29313-29319 (2013) (Year: 2013). [cited by examiner]
R. Petra et al., “HWCVD a-Si:H interlayer slope waveguide coupler for multilayer silicon photonics platform,” 2017 IEEE 14th International Conference on Group IV Photonics (GFP), Berlin, Germany, 2017, pp. 47-48, doi: 1… [cited by examiner]
I. Moerman, P. P. Van Daele and P. M. Demeester, “A review on fabrication technologies for the monolithic integration of tapers with III-V semiconductor devices,” in IEEE Journal of Selected Topics in Quantum Electronic… [cited by examiner]
GB Examination Report for Application No. GB1905698.5 dated Sep. 22, 2020, 5 pages. [cited by applicant]
Search Report from UK IPO, Application No. GB1905698.5, dated Oct. 25, 2019, 3 pages. [cited by applicant]
International Search Report and Written Opinion, International Application No. PCT/EP2020/061483, European International Searching Authority, dated Jul. 13, 2020, 12 pages. [cited by applicant]
International Preliminary Report on Patentability, International Application No. PCT/EP2020/061483, International Searching Authority, dated Sep. 28, 2021, 7 pages. [cited by applicant]
Chun-Wei Liao, et al: “Fiber-Core-Matched Three-Dimensional Adiabatic Tapered Couplers for Integrated Photonic Devices”, Journal of Lightwave Technology, IEEE, vol. 29, No. 5, Mar. 2011, 5 pages. [cited by applicant]
Snyder, Bradley, et al: “Packaging and Assembly Challenges for 50G Silicon Photonics Interposers.” 2018 Optical Fiber Communications Conference and Exposition (OFC). IEEE, 2018. [cited by applicant]
Ku, Kai-Ning, and Ming-Chang M. Lee: “Cascade of two opposite tapers for butt-coupling between fibers and silicon photonic wires with large misalignment tolerance and low polarization dependency.” Optical Fiber Communic… [cited by applicant]
Shoji, T., et al: “Low loss mode size converter from 0.3 μm square Si wire waveguides to single-mode fibers.” Electronics Letters 38.25 (2002): 1669-1670. [cited by applicant]
Choo, Hyuck, et al: “Nano-focusing in a metal-insulator-metal gap plasmon waveguide with a three-dimensional linear taper.” Nature Photonics 6.12 (2012): 838. [cited by applicant]
Fang, Qing, et al: “Low loss fiber-to-waveguide converter with a 3-D functional taper for silicon photonics.” IEEE Photonics Technology Letters 28.22 (2016): 2533-2536. [cited by applicant]
Fang, Na, et al: “Three-dimensional tapered spot-size converter based on (111) silicon-on-insulator.” IEEE Photonics Technology Letters 21.12 (2009): 820-822. [cited by applicant]
Yang, Zhifeng, et al: “Fabrication and characterization of integrated three-dimensional linear taper on silicon-on-insulator.” Optical Engineering 48.3 (2009): 030503. [cited by applicant]
Li, Ling-Han, et al: “Monolithically integrated low-loss three-dimensional spot-size converter and silicon photonic waveguides constructed by nano-tuned Bosch process and oxidation.” Journal of Micro/Nanolithography, ME… [cited by applicant]
Fritze, M., et al: “Fabrication of three-dimensional mode converters for silicon-based integrated optics.” Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and… [cited by applicant]
Holly, Roman, et al: “Fabrication of silicon 3D taper structures for optical fiber to chip interface.” Microelectronic engineering84.5-8 (2007): 1248-1251. [cited by applicant]
I Day, I Evans, A Knights et al: “Tapered silicon waveguides for low-insertion-loss highly efficient high-speed electronic variable attenuators”, in IEEE OFC 2003. [cited by applicant]
Cheben P et al: “Subwavelength waveguide grating for mode conversion and light coupling in integrated optics” Optics Express v14. n11, p. 4695-4702. [cited by applicant]
Gupta, Ramesh K., and Bijoy K. Das: “Multi-input and multi-output soi (MIMO-SOI) platform for silicon photonics.” CSI transactions on ICT 5.2 (2017): 189-193. [cited by applicant]
Choudhury, Anm Masum, et al: “Method of improving light coupling efficiency between optical fibers and silicon waveguides.” IEEE photonics technology letters 17.9 (2005): 1881-1883. [cited by applicant]
Simon Groblacher et al: “Highly efficient coupling from an optical fiber to a nanoscale silicon optomechanical cavity” Applied Physics Letters, 103, 181104, 2013. [cited by applicant]
Saeed Khan et al: “Low-loss, high-bandwidth fiber-to-chip coupling using capped adiabatic tapered fibers” National Institute of Standards and Technology, 2020. [cited by applicant]
Oscar A. Jimenez Gordillo et al: “Bridging Between Si and Few-Mode Fiber Higher Order Modes” Department of Electrical Engineering, 2020. [cited by applicant]
L. Chen et al: 3D Vertical Coupler Array for 4-Way Multi-Core Fiber-To-Chip Coupling by Two-Photon Lithography, State Key Laboratory of Optoelectronic Materials and Technologies, 2020. [cited by applicant]
R. Kou et al: “III-V/Si Adiabatic-Crossing Taper Structure Designed for u-Transfer Printing” 2020. [cited by applicant]
M-J Picard et al: “CMOS-compatible spot-size converter for optical fiber to sub-um silicon waveguide coupling with low-loss low-wavelength dependence and high tolerance to misalignment” SPIE 2016. [cited by applicant]
K. Kasaya et al: “A Simple Laterally Tapered Waveguide for Low-Loss Coupling to Single-Mode Fibers” IEEE Photonics Technology Letters, vol. 5, No. 3 1993. [cited by applicant]
Y. Maegami et al: “Completely CMOS compatible SiN-waveguide-based fiber coupling structure for Si wire waveguides” Optics Express vol. 24, No. 15 2016. [cited by applicant]
E. F. Perez at al: “Robust and automated direct on-axis laser writing of coupling elements for photonic chips” Dept of Physics 2019. [cited by applicant]
J. V. Galan et al: “Polarization insensitive low-loss coupling technique between SOI waveguides and high mode field diameter single-mode fibers” Optical Society of America 2007. [cited by applicant]
Qing Fang et al: “Suspended optical fiber-to-waveguide mode size converter for Silicon photonics” Optical Society of America 2010. [cited by applicant]
Pavel Cheben et al: “Broadband polarization independent nanophotonic coupler for silicon waveguides with ultra-high efficiency” Optical Society of America 2015. [cited by applicant]
Jhaozhi Luo et al: “Low-loss and broadband fiber-to-chip coupler by 3D fabrication on a silicon photonic platform” Optics Letters, vol. 45, No. 5 2020. [cited by applicant]
T. G. Tiecke et al: “Efficient fiber-optical interface for nanophotonic devices” Optica 2015. [cited by applicant]
Weifeng Jiang & B.M. Azizur Rahman: “Phase-matched multi-layer-based polarization-independent spot-size converter for silicon nanowire” Nature 2019. [cited by applicant]
EP Examination Report—Communication pursuant to Article 94(3) EPC, Application No. 20721567.4, European Patent Office, mailed on May 2, 2024, 5 pages. [cited by applicant]
1st Office Action, Chinese Application No. 202080031337.2, CNIPA Patent Office, dated Jan. 2, 2024, English Translation, 15 pages. [cited by applicant]
NPL: Yanagawa, et al., “Index and Dimensional Taper and Its Application to Photonic Devices”, Journal of Lightwave Technology, vol. 10, No. 5, May 1992, 6 pages. [cited by applicant]